vgal.tan.qmsg

实现模拟阴极射线管的彩色显示的行扫描和场扫描

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "FS\[3\] " "Info: Detected ripple clock \"FS\[3\]\" as buffer" {  } { { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 11 -1 0 } } { "d:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "FS\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "CC\[4\] " "Info: Detected ripple clock \"CC\[4\]\" as buffer" {  } { { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 49 -1 0 } } { "d:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CC\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register LL\[0\] register LL\[5\] 227.12 MHz 4.403 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 227.12 MHz between source register \"LL\[0\]\" and destination register \"LL\[5\]\" (period= 4.403 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.142 ns + Longest register register " "Info: + Longest register to register delay is 4.142 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LL\[0\] 1 REG LC_X16_Y12_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y12_N2; Fanout = 8; REG Node = 'LL\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { LL[0] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.292 ns) + CELL(0.564 ns) 1.856 ns Add3~147 2 COMB LC_X16_Y11_N0 2 " "Info: 2: + IC(1.292 ns) + CELL(0.564 ns) = 1.856 ns; Loc. = LC_X16_Y11_N0; Fanout = 2; COMB Node = 'Add3~147'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.856 ns" { LL[0] Add3~147 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.934 ns Add3~149 3 COMB LC_X16_Y11_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.934 ns; Loc. = LC_X16_Y11_N1; Fanout = 2; COMB Node = 'Add3~149'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { Add3~147 Add3~149 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 2.012 ns Add3~145 4 COMB LC_X16_Y11_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 2.012 ns; Loc. = LC_X16_Y11_N2; Fanout = 2; COMB Node = 'Add3~145'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { Add3~149 Add3~145 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 2.090 ns Add3~143 5 COMB LC_X16_Y11_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 2.090 ns; Loc. = LC_X16_Y11_N3; Fanout = 2; COMB Node = 'Add3~143'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { Add3~145 Add3~143 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 2.268 ns Add3~141 6 COMB LC_X16_Y11_N4 4 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 2.268 ns; Loc. = LC_X16_Y11_N4; Fanout = 4; COMB Node = 'Add3~141'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Add3~143 Add3~141 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.889 ns Add3~138 7 COMB LC_X16_Y11_N5 1 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.889 ns; Loc. = LC_X16_Y11_N5; Fanout = 1; COMB Node = 'Add3~138'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { Add3~141 Add3~138 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.478 ns) 4.142 ns LL\[5\] 8 REG LC_X17_Y11_N8 9 " "Info: 8: + IC(0.775 ns) + CELL(0.478 ns) = 4.142 ns; Loc. = LC_X17_Y11_N8; Fanout = 9; REG Node = 'LL\[5\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.253 ns" { Add3~138 LL[5] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.075 ns ( 50.10 % ) " "Info: Total cell delay = 2.075 ns ( 50.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.067 ns ( 49.90 % ) " "Info: Total interconnect delay = 2.067 ns ( 49.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.142 ns" { LL[0] Add3~147 Add3~149 Add3~145 Add3~143 Add3~141 Add3~138 LL[5] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "4.142 ns" { LL[0] {} Add3~147 {} Add3~149 {} Add3~145 {} Add3~143 {} Add3~141 {} Add3~138 {} LL[5] {} } { 0.000ns 1.292ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.775ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.078ns 0.178ns 0.621ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 11.973 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 11.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns FS\[3\] 2 REG LC_X8_Y6_N2 8 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'FS\[3\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { CLK FS[3] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.456 ns) + CELL(0.935 ns) 7.355 ns CC\[4\] 3 REG LC_X11_Y6_N9 15 " "Info: 3: + IC(3.456 ns) + CELL(0.935 ns) = 7.355 ns; Loc. = LC_X11_Y6_N9; Fanout = 15; REG Node = 'CC\[4\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.391 ns" { FS[3] CC[4] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.907 ns) + CELL(0.711 ns) 11.973 ns LL\[5\] 4 REG LC_X17_Y11_N8 9 " "Info: 4: + IC(3.907 ns) + CELL(0.711 ns) = 11.973 ns; Loc. = LC_X17_Y11_N8; Fanout = 9; REG Node = 'LL\[5\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.618 ns" { CC[4] LL[5] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 33.83 % ) " "Info: Total cell delay = 4.050 ns ( 33.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.923 ns ( 66.17 % ) " "Info: Total interconnect delay = 7.923 ns ( 66.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.973 ns" { CLK FS[3] CC[4] LL[5] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.973 ns" { CLK {} CLK~out0 {} FS[3] {} CC[4] {} LL[5] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.907ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 11.973 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 11.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns FS\[3\] 2 REG LC_X8_Y6_N2 8 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'FS\[3\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { CLK FS[3] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.456 ns) + CELL(0.935 ns) 7.355 ns CC\[4\] 3 REG LC_X11_Y6_N9 15 " "Info: 3: + IC(3.456 ns) + CELL(0.935 ns) = 7.355 ns; Loc. = LC_X11_Y6_N9; Fanout = 15; REG Node = 'CC\[4\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.391 ns" { FS[3] CC[4] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.907 ns) + CELL(0.711 ns) 11.973 ns LL\[0\] 4 REG LC_X16_Y12_N2 8 " "Info: 4: + IC(3.907 ns) + CELL(0.711 ns) = 11.973 ns; Loc. = LC_X16_Y12_N2; Fanout = 8; REG Node = 'LL\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.618 ns" { CC[4] LL[0] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 33.83 % ) " "Info: Total cell delay = 4.050 ns ( 33.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.923 ns ( 66.17 % ) " "Info: Total interconnect delay = 7.923 ns ( 66.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.973 ns" { CLK FS[3] CC[4] LL[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.973 ns" { CLK {} CLK~out0 {} FS[3] {} CC[4] {} LL[0] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.907ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.973 ns" { CLK FS[3] CC[4] LL[5] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.973 ns" { CLK {} CLK~out0 {} FS[3] {} CC[4] {} LL[5] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.907ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.973 ns" { CLK FS[3] CC[4] LL[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.973 ns" { CLK {} CLK~out0 {} FS[3] {} CC[4] {} LL[0] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.907ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 58 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 58 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.142 ns" { LL[0] Add3~147 Add3~149 Add3~145 Add3~143 Add3~141 Add3~138 LL[5] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "4.142 ns" { LL[0] {} Add3~147 {} Add3~149 {} Add3~145 {} Add3~143 {} Add3~141 {} Add3~138 {} LL[5] {} } { 0.000ns 1.292ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.775ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.078ns 0.178ns 0.621ns 0.478ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.973 ns" { CLK FS[3] CC[4] LL[5] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.973 ns" { CLK {} CLK~out0 {} FS[3] {} CC[4] {} LL[5] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.907ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.973 ns" { CLK FS[3] CC[4] LL[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.973 ns" { CLK {} CLK~out0 {} FS[3] {} CC[4] {} LL[0] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.907ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "MD register register MMD\[1\] MMD\[0\] 275.03 MHz Internal " "Info: Clock \"MD\" Internal fmax is restricted to 275.03 MHz between source register \"MMD\[1\]\" and destination register \"MMD\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.064 ns + Longest register register " "Info: + Longest register to register delay is 1.064 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns MMD\[1\] 1 REG LC_X15_Y11_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y11_N9; Fanout = 4; REG Node = 'MMD\[1\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { MMD[1] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.586 ns) + CELL(0.478 ns) 1.064 ns MMD\[0\] 2 REG LC_X15_Y11_N5 8 " "Info: 2: + IC(0.586 ns) + CELL(0.478 ns) = 1.064 ns; Loc. = LC_X15_Y11_N5; Fanout = 8; REG Node = 'MMD\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.064 ns" { MMD[1] MMD[0] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 44.92 % ) " "Info: Total cell delay = 0.478 ns ( 44.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.586 ns ( 55.08 % ) " "Info: Total interconnect delay = 0.586 ns ( 55.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.064 ns" { MMD[1] MMD[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "1.064 ns" { MMD[1] {} MMD[0] {} } { 0.000ns 0.586ns } { 0.000ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MD destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"MD\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MD 1 CLK PIN_16 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 5; CLK Node = 'MD'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { MD } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns MMD\[0\] 2 REG LC_X15_Y11_N5 8 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y11_N5; Fanout = 8; REG Node = 'MMD\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { MD MMD[0] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { MD MMD[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { MD {} MD~out0 {} MMD[0] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MD source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"MD\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MD 1 CLK PIN_16 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 5; CLK Node = 'MD'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { MD } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns MMD\[1\] 2 REG LC_X15_Y11_N9 4 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y11_N9; Fanout = 4; REG Node = 'MMD\[1\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { MD MMD[1] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { MD MMD[1] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { MD {} MD~out0 {} MMD[1] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { MD MMD[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { MD {} MD~out0 {} MMD[0] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { MD MMD[1] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { MD {} MD~out0 {} MMD[1] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.064 ns" { MMD[1] MMD[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "1.064 ns" { MMD[1] {} MMD[0] {} } { 0.000ns 0.586ns } { 0.000ns 0.478ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { MD MMD[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { MD {} MD~out0 {} MMD[0] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { MD MMD[1] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { MD {} MD~out0 {} MMD[1] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { MMD[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { MMD[0] {} } {  } {  } "" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 22 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK B LL\[2\] 23.851 ns register " "Info: tco from clock \"CLK\" to destination pin \"B\" through register \"LL\[2\]\" is 23.851 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 11.973 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 11.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns FS\[3\] 2 REG LC_X8_Y6_N2 8 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'FS\[3\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { CLK FS[3] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.456 ns) + CELL(0.935 ns) 7.355 ns CC\[4\] 3 REG LC_X11_Y6_N9 15 " "Info: 3: + IC(3.456 ns) + CELL(0.935 ns) = 7.355 ns; Loc. = LC_X11_Y6_N9; Fanout = 15; REG Node = 'CC\[4\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.391 ns" { FS[3] CC[4] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.907 ns) + CELL(0.711 ns) 11.973 ns LL\[2\] 4 REG LC_X17_Y11_N1 6 " "Info: 4: + IC(3.907 ns) + CELL(0.711 ns) = 11.973 ns; Loc. = LC_X17_Y11_N1; Fanout = 6; REG Node = 'LL\[2\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.618 ns" { CC[4] LL[2] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 33.83 % ) " "Info: Total cell delay = 4.050 ns ( 33.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.923 ns ( 66.17 % ) " "Info: Total interconnect delay = 7.923 ns ( 66.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.973 ns" { CLK FS[3] CC[4] LL[2] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.973 ns" { CLK {} CLK~out0 {} FS[3] {} CC[4] {} LL[2] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.907ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 58 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.654 ns + Longest register pin " "Info: + Longest register to pin delay is 11.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LL\[2\] 1 REG LC_X17_Y11_N1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y11_N1; Fanout = 6; REG Node = 'LL\[2\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { LL[2] } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.240 ns) + CELL(0.590 ns) 1.830 ns GRB~2104 2 COMB LC_X15_Y11_N6 1 " "Info: 2: + IC(1.240 ns) + CELL(0.590 ns) = 1.830 ns; Loc. = LC_X15_Y11_N6; Fanout = 1; COMB Node = 'GRB~2104'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.830 ns" { LL[2] GRB~2104 } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.114 ns) 2.367 ns GRB~2105 3 COMB LC_X15_Y11_N8 1 " "Info: 3: + IC(0.423 ns) + CELL(0.114 ns) = 2.367 ns; Loc. = LC_X15_Y11_N8; Fanout = 1; COMB Node = 'GRB~2105'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.537 ns" { GRB~2104 GRB~2105 } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.059 ns) + CELL(0.292 ns) 4.718 ns GRB~2099 4 COMB LC_X15_Y11_N2 1 " "Info: 4: + IC(2.059 ns) + CELL(0.292 ns) = 4.718 ns; Loc. = LC_X15_Y11_N2; Fanout = 1; COMB Node = 'GRB~2099'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.351 ns" { GRB~2105 GRB~2099 } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.719 ns) + CELL(0.590 ns) 7.027 ns GRB~2103 5 COMB LC_X12_Y7_N5 1 " "Info: 5: + IC(1.719 ns) + CELL(0.590 ns) = 7.027 ns; Loc. = LC_X12_Y7_N5; Fanout = 1; COMB Node = 'GRB~2103'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.309 ns" { GRB~2099 GRB~2103 } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.503 ns) + CELL(2.124 ns) 11.654 ns B 6 PIN PIN_11 0 " "Info: 6: + IC(2.503 ns) + CELL(2.124 ns) = 11.654 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'B'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.627 ns" { GRB~2103 B } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.710 ns ( 31.83 % ) " "Info: Total cell delay = 3.710 ns ( 31.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.944 ns ( 68.17 % ) " "Info: Total interconnect delay = 7.944 ns ( 68.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.654 ns" { LL[2] GRB~2104 GRB~2105 GRB~2099 GRB~2103 B } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.654 ns" { LL[2] {} GRB~2104 {} GRB~2105 {} GRB~2099 {} GRB~2103 {} B {} } { 0.000ns 1.240ns 0.423ns 2.059ns 1.719ns 2.503ns } { 0.000ns 0.590ns 0.114ns 0.292ns 0.590ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.973 ns" { CLK FS[3] CC[4] LL[2] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.973 ns" { CLK {} CLK~out0 {} FS[3] {} CC[4] {} LL[2] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.907ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.654 ns" { LL[2] GRB~2104 GRB~2105 GRB~2099 GRB~2103 B } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "11.654 ns" { LL[2] {} GRB~2104 {} GRB~2105 {} GRB~2099 {} GRB~2103 {} B {} } { 0.000ns 1.240ns 0.423ns 2.059ns 1.719ns 2.503ns } { 0.000ns 0.590ns 0.114ns 0.292ns 0.590ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}