int_osc.v

这是一个关于晶震的一个verilog 源代码,希望对新手有用

/************************************************************************************************************************************************************************************************
 Using Internal Oscillator
 December 2006
************************************************************************************************************************************************************************************************/
// Top Level module
`timescale 1 ps / 1 ps
module int_osc (sw9, d2, d3, d5, d6, d8, d10, d11, d12, d4_1, d4_2, d7_1, d7_2, d9_1, d9_2, osc, clk);

/* Input is push button switch and outputs are leds */
input sw9; 
output d2, d3, d5, d6, d8, d10, d11, d12, d4_1, d4_2, d7_1, d7_2, d9_1, d9_2, clk, osc;

wire osc_w, oscena_w, clk_w;
assign oscena_w =(sw9);      // Enable the oscillator
assign osc = osc_w;
assign clk= clk_w;
counter cntr (.ct0(d2), .ct0_2(d4_1), .ct3(d3), .ct4(d4_2), .ct6(d5), .ct8(d7_1), .ct9(d6), .ct12(d8), .ct12_2(d7_2), .ct15(d10), .ct16(d9_1), .ct18(d11), .ct20(d9_2), .ct21(d12), .clk(clk_w));
altufm_osc0_altufm_osc_1p3 ufm (.osc(osc_w), .oscena(oscena_w)); 
reduced_osc rosc (.osc(osc_w), .clk(clk_w));

endmodule

/***********************************************************************************************************************************************************************************************
 Module for displaying running LED pattern
**************************************************************************************************************************/
module counter (clk, ct0, ct0_2, ct3, ct6, ct9, ct12, ct15, ct18, ct21, ct4, ct8, ct12_2, ct16, ct20);

/* Input is the outputof the reduced oscillator module
 * Outputs are the Leds
 * A single colour Led is turned on for every third count
 * A Bi colour Led is turned on for every fourth count    */
input clk;
output ct0, ct0_2, ct3, ct6, ct9, ct12, ct12_2, ct15, ct18, ct21, ct4, ct8, ct16, ct20;

reg ct0, ct0_2, ct3, ct6, ct9, ct12, ct12_2, ct15, ct18, ct21, ct4, ct8, ct16, ct20;
reg [4:0] count;

initial
begin
count = 0;
end

always @ (posedge clk) begin 
	count <= count + 1;
	if (count == 5'b00000) ct0 <= 0; else ct0 <= 1; 
	if (count == 5'b00000) ct0_2 <= 0; else ct0_2 <= 1;
	if (count == 5'b00011) ct3 <= 0; else ct3 <= 1;
	if (count == 5'b00100) ct4 <= 0; else ct4 <= 1;
	if (count == 5'b00110) ct6 <= 0; else ct6 <= 1;
	if (count == 5'b01000) ct8 <= 0; else ct8 <= 1;
	if (count == 5'b01001) ct9 <= 0; else ct9 <= 1;
	if (count == 5'b01100) ct12 <= 0; else ct12 <= 1; 
	if (count == 5'b01100) ct12_2 <= 0; else ct12_2 <= 1;
	if (count == 5'b01111) ct15 <= 0; else ct15 <= 1;
	if (count == 5'b10000) ct16 <= 0; else ct16 <= 1;
	if (count == 5'b10010) ct18 <= 0; else ct18 <= 1;
	if (count == 5'b10100) ct20 <= 0; else ct20 <= 1;
	if (count == 5'b10101) ct21 <= 0; else ct21 <= 1;
	if (count == 5'b10111) count <= 4'b0;
end

endmodule
	
/**************************************************************************************************************************************************/
/* Megafunction for Internal oscillator */

`timescale 1 ps / 1 ps
//synopsys translate_on
module  altufm_osc0_altufm_osc_1p3
	( 
	osc,
	oscena) /* synthesis synthesis_clearbox=1 */;
	output   osc;
	input   oscena;

	wire  wire_maxii_ufm_block1_osc;

	maxii_ufm   maxii_ufm_block1
	( 
	.arclk(1'b0),
	.ardin(1'b0),
	.arshft(1'b0),
	.bgpbusy(),
	.busy(),
	.drclk(1'b0),
	.drdout(),
	.drshft(1'b0),
	.osc(wire_maxii_ufm_block1_osc),
	.oscena(oscena)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.drdin(1'b0),
	.erase(1'b0),
	.program(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.ctrl_bgpbusy(),
	.devclrn(),
	.devpor(),
	.sbdin(),
	.sbdout()
	// synopsys translate_on
	);
	defparam
		maxii_ufm_block1.address_width = 9,
		maxii_ufm_block1.osc_sim_setting = 300000,
		maxii_ufm_block1.lpm_type = "maxii_ufm";
	assign
		osc = wire_maxii_ufm_block1_osc;
endmodule //altufm_osc0_altufm_osc_1p3
//VALID FILE

/****************************************************************************************************************************
 Module to reduce the frequency of internal oscillator
****************************************************************************************************************************/
module reduced_osc (osc, clk);

input osc;               // Output of internal osc
output clk;              // Reduced frequency clock

reg [15:0] count;
reg clk;

initial
begin
count = 0;
end

always @ (posedge osc) begin
count = count + 1;
clk <= count[15];
end

endmodule

/***************************************************************************************************************************/