sram.tan.qmsg

静态随机存储器(SRAM)设计VHDL代码

{ "Info" "ITDB_TSU_RESULT" "sram~82 din\[2\] cs 6.322 ns register " "Info: tsu for register \"sram~82\" (data pin = \"din\[2\]\", clock pin = \"cs\") is 6.322 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.051 ns + Longest pin register " "Info: + Longest pin to register delay is 9.051 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns din\[2\] 1 PIN PIN_238 16 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_238; Fanout = 16; PIN Node = 'din\[2\]'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { din[2] } "NODE_NAME" } } { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.134 ns) + CELL(0.442 ns) 9.051 ns sram~82 2 REG LC_X8_Y11_N7 1 " "Info: 2: + IC(7.134 ns) + CELL(0.442 ns) = 9.051 ns; Loc. = LC_X8_Y11_N7; Fanout = 1; REG Node = 'sram~82'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.576 ns" { din[2] sram~82 } "NODE_NAME" } } { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.917 ns ( 21.18 % ) " "Info: Total cell delay = 1.917 ns ( 21.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.134 ns ( 78.82 % ) " "Info: Total interconnect delay = 7.134 ns ( 78.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.051 ns" { din[2] sram~82 } "NODE_NAME" } } { "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.051 ns" { din[2] din[2]~out0 sram~82 } { 0.000ns 0.000ns 7.134ns } { 0.000ns 1.475ns 0.442ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.871 ns + " "Info: + Micro setup delay of destination is 0.871 ns" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cs destination 3.600 ns - Shortest register " "Info: - Shortest clock path from clock \"cs\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cs 1 CLK PIN_38 17 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_38; Fanout = 17; CLK Node = 'cs'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { cs } "NODE_NAME" } } { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.543 ns) + CELL(0.292 ns) 3.304 ns rtl~7 2 COMB LC_X8_Y11_N6 8 " "Info: 2: + IC(1.543 ns) + CELL(0.292 ns) = 3.304 ns; Loc. = LC_X8_Y11_N6; Fanout = 8; COMB Node = 'rtl~7'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.835 ns" { cs rtl~7 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.600 ns sram~82 3 REG LC_X8_Y11_N7 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 3.600 ns; Loc. = LC_X8_Y11_N7; Fanout = 1; REG Node = 'sram~82'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { rtl~7 sram~82 } "NODE_NAME" } } { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.875 ns ( 52.08 % ) " "Info: Total cell delay = 1.875 ns ( 52.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.725 ns ( 47.92 % ) " "Info: Total interconnect delay = 1.725 ns ( 47.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { cs rtl~7 sram~82 } "NODE_NAME" } } { "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { cs cs~out0 rtl~7 sram~82 } { 0.000ns 0.000ns 1.543ns 0.182ns } { 0.000ns 1.469ns 0.292ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.051 ns" { din[2] sram~82 } "NODE_NAME" } } { "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.051 ns" { din[2] din[2]~out0 sram~82 } { 0.000ns 0.000ns 7.134ns } { 0.000ns 1.475ns 0.442ns } "" } } { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { cs rtl~7 sram~82 } "NODE_NAME" } } { "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { cs cs~out0 rtl~7 sram~82 } { 0.000ns 0.000ns 1.543ns 0.182ns } { 0.000ns 1.469ns 0.292ns 0.114ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "adr\[1\] dout\[4\] sram~52 25.271 ns register " "Info: tco from clock \"adr\[1\]\" to destination pin \"dout\[4\]\" through register \"sram~52\" is 25.271 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "adr\[1\] source 15.943 ns + Longest register " "Info: + Longest clock path from clock \"adr\[1\]\" to source register is 15.943 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns adr\[1\] 1 CLK PIN_21 46 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_21; Fanout = 46; CLK Node = 'adr\[1\]'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { adr[1] } "NODE_NAME" } } { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.940 ns) + CELL(0.292 ns) 7.701 ns sram~443 2 COMB LC_X45_Y13_N8 1 " "Info: 2: + IC(5.940 ns) + CELL(0.292 ns) = 7.701 ns; Loc. = LC_X45_Y13_N8; Fanout = 1; COMB Node = 'sram~443'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.232 ns" { adr[1] sram~443 } "NODE_NAME" } } { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 7.997 ns rtl~11 3 COMB LC_X45_Y13_N9 8 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 7.997 ns; Loc. = LC_X45_Y13_N9; Fanout = 8; COMB Node = 'rtl~11'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { sram~443 rtl~11 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.832 ns) + CELL(0.114 ns) 15.943 ns sram~52 4 REG LC_X13_Y14_N3 1 " "Info: 4: + IC(7.832 ns) + CELL(0.114 ns) = 15.943 ns; Loc. = LC_X13_Y14_N3; Fanout = 1; REG Node = 'sram~52'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.946 ns" { rtl~11 sram~52 } "NODE_NAME" } } { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.989 ns ( 12.48 % ) " "Info: Total cell delay = 1.989 ns ( 12.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.954 ns ( 87.52 % ) " "Info: Total interconnect delay = 13.954 ns ( 87.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "15.943 ns" { adr[1] sram~443 rtl~11 sram~52 } "NODE_NAME" } } { "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "15.943 ns" { adr[1] adr[1]~out0 sram~443 rtl~11 sram~52 } { 0.000ns 0.000ns 5.940ns 0.182ns 7.832ns } { 0.000ns 1.469ns 0.292ns 0.114ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.328 ns + Longest register pin " "Info: + Longest register to pin delay is 9.328 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sram~52 1 REG LC_X13_Y14_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y14_N3; Fanout = 1; REG Node = 'sram~52'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { sram~52 } "NODE_NAME" } } { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.540 ns) + CELL(0.114 ns) 1.654 ns sram~397 2 COMB LC_X10_Y12_N4 1 " "Info: 2: + IC(1.540 ns) + CELL(0.114 ns) = 1.654 ns; Loc. = LC_X10_Y12_N4; Fanout = 1; COMB Node = 'sram~397'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.654 ns" { sram~52 sram~397 } "NODE_NAME" } } { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.442 ns) 2.533 ns sram~398 3 COMB LC_X10_Y12_N7 1 " "Info: 3: + IC(0.437 ns) + CELL(0.442 ns) = 2.533 ns; Loc. = LC_X10_Y12_N7; Fanout = 1; COMB Node = 'sram~398'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.879 ns" { sram~397 sram~398 } "NODE_NAME" } } { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.207 ns) + CELL(0.442 ns) 4.182 ns sram~401 4 COMB LC_X9_Y11_N1 1 " "Info: 4: + IC(1.207 ns) + CELL(0.442 ns) = 4.182 ns; Loc. = LC_X9_Y11_N1; Fanout = 1; COMB Node = 'sram~401'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.649 ns" { sram~398 sram~401 } "NODE_NAME" } } { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.038 ns) + CELL(2.108 ns) 9.328 ns dout\[4\] 5 PIN PIN_234 0 " "Info: 5: + IC(3.038 ns) + CELL(2.108 ns) = 9.328 ns; Loc. = PIN_234; Fanout = 0; PIN Node = 'dout\[4\]'" {  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.146 ns" { sram~401 dout[4] } "NODE_NAME" } } { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.106 ns ( 33.30 % ) " "Info: Total cell delay = 3.106 ns ( 33.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.222 ns ( 66.70 % ) " "Info: Total interconnect delay = 6.222 ns ( 66.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.328 ns" { sram~52 sram~397 sram~398 sram~401 dout[4] } "NODE_NAME" } } { "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.328 ns" { sram~52 sram~397 sram~398 sram~401 dout[4] } { 0.000ns 1.540ns 0.437ns 1.207ns 3.038ns } { 0.000ns 0.114ns 0.442ns 0.442ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "15.943 ns" { adr[1] sram~443 rtl~11 sram~52 } "NODE_NAME" } } { "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "15.943 ns" { adr[1] adr[1]~out0 sram~443 rtl~11 sram~52 } { 0.000ns 0.000ns 5.940ns 0.182ns 7.832ns } { 0.000ns 1.469ns 0.292ns 0.114ns 0.114ns } "" } } { "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.328 ns" { sram~52 sram~397 sram~398 sram~401 dout[4] } "NODE_NAME" } } { "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.328 ns" { sram~52 sram~397 sram~398 sram~401 dout[4] } { 0.000ns 1.540ns 0.437ns 1.207ns 3.038ns } { 0.000ns 0.114ns 0.442ns 0.442ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}