sram.tan.qmsg

静态随机存储器(SRAM)设计VHDL代码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "adr\[1\] " "Info: Assuming node \"adr\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 14 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "adr\[0\] " "Info: Assuming node \"adr\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 14 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "adr\[2\] " "Info: Assuming node \"adr\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 14 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "adr\[3\] " "Info: Assuming node \"adr\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 14 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "rd " "Info: Assuming node \"rd\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 13 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "cs " "Info: Assuming node \"cs\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 13 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "wr " "Info: Assuming node \"wr\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 13 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "32 " "Warning: Found 32 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "rtl~15 " "Info: Detected gated clock \"rtl~15\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~15" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~447 " "Info: Detected gated clock \"sram~447\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~447" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~14 " "Info: Detected gated clock \"rtl~14\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~14" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~446 " "Info: Detected gated clock \"sram~446\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~446" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~13 " "Info: Detected gated clock \"rtl~13\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~13" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~445 " "Info: Detected gated clock \"sram~445\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~445" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~12 " "Info: Detected gated clock \"rtl~12\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~12" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~444 " "Info: Detected gated clock \"sram~444\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~444" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~11 " "Info: Detected gated clock \"rtl~11\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~11" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~443 " "Info: Detected gated clock \"sram~443\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~443" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~10 " "Info: Detected gated clock \"rtl~10\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~10" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~442 " "Info: Detected gated clock \"sram~442\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~442" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~9 " "Info: Detected gated clock \"rtl~9\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~9" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~441 " "Info: Detected gated clock \"sram~441\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~441" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~8 " "Info: Detected gated clock \"rtl~8\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~8" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~440 " "Info: Detected gated clock \"sram~440\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~440" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~7 " "Info: Detected gated clock \"rtl~7\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~7" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~439 " "Info: Detected gated clock \"sram~439\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~439" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~6 " "Info: Detected gated clock \"rtl~6\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~6" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~438 " "Info: Detected gated clock \"sram~438\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~438" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~5 " "Info: Detected gated clock \"rtl~5\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~5" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~437 " "Info: Detected gated clock \"sram~437\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~437" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~4 " "Info: Detected gated clock \"rtl~4\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~436 " "Info: Detected gated clock \"sram~436\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~436" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~3 " "Info: Detected gated clock \"rtl~3\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~3" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~435 " "Info: Detected gated clock \"sram~435\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~435" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~2 " "Info: Detected gated clock \"rtl~2\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~2" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~434 " "Info: Detected gated clock \"sram~434\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~434" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~1 " "Info: Detected gated clock \"rtl~1\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~433 " "Info: Detected gated clock \"sram~433\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~433" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~0 " "Info: Detected gated clock \"rtl~0\" as buffer" {  } { { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "rtl~0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "sram~432 " "Info: Detected gated clock \"sram~432\" as buffer" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 23 -1 0 } } { "g:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "sram~432" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}