sram.map.qmsg

静态随机存储器(SRAM)设计VHDL代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Web Edition " "Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 04 10:04:13 2007 " "Info: Processing started: Sun Mar 04 10:04:13 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sram -c sram " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sram -c sram" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sram-behave " "Info: Found design unit 1: sram-behave" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sram " "Info: Found entity 1: sram" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sram " "Info: Elaborating entity \"sram\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sram sram.vhd(38) " "Warning (10492): VHDL Process Statement warning at sram.vhd(38): signal \"sram\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "sram.vhd" "" { Text "L:/EDA技术资料/模块程序（便于调用）/静态随机存储器(SRAM)设计/sram.vhd" 38 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "272 " "Info: Implemented 272 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "15 " "Info: Implemented 15 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "241 " "Info: Implemented 241 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "132 " "Info: Allocated 132 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 04 10:04:19 2007 " "Info: Processing ended: Sun Mar 04 10:04:19 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}