top_level_tb.vhd

Serial ADC Interface write in VHDL based on xilinx cpld

-- **************************************************************
--
-- Owner:	Xilinx Inc.
-- File:  	top_level_tb.vhd
--
-- Purpose: 	Test bench for TOP_LEVEL entity.  Checks that
--		data is sent to ADC from configure registers.  Checks
--		SRAM address for writing data from ADC to SRAM.
--
-- **************************************************************


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY TOP_LEVEL_TB IS
END TOP_LEVEL_TB;

ARCHITECTURE BEHAVE OF TOP_LEVEL_TB IS 

-- ******************** CONSTANT DECLARATIONS ***********************

constant HALFCLKPERIOD	: 	time	:= 200 nS;

-- Component Declaration
	Component TOP_LEVEL
		port(

	SP_CS0n	 		: in 		STD_LOGIC;
	SP_CS1n   		: in 		STD_LOGIC;
	SP_WEn  		: in 		STD_LOGIC;
	SP_OEn			: in 		STD_LOGIC;
	SP_D			: inout 	STD_LOGIC_VECTOR(15 DOWNTO 0);
	SP_A			: in 	  	STD_LOGIC_VECTOR(23 DOWNTO 1);
	SP_A_0 			: out   	STD_LOGIC;
	--SPRING_RESETn		: in 		STD_LOGIC;
	CHIP3_EN		: out 		STD_LOGIC;
	A			: out 		STD_LOGIC_VECTOR(22 DOWNTO 0);
	D			: inout 	STD_LOGIC_VECTOR(15 DOWNTO 0);
	FLASH_CS0n		: out 		STD_LOGIC;
	FLASH_WR_PROTECT	: out 		STD_LOGIC;
	SRAM_CS1n		: inout 	STD_LOGIC;
	OEn			: out 		STD_LOGIC;
	RWn			: inout 	STD_LOGIC;

	IO13			: out 		STD_LOGIC;

	SRAM_UPPER_BYTEn	: out 		STD_LOGIC;
	SRAM_LOW_BYTEn		: out 		STD_LOGIC;

			
	--ADS7870 Signals
	Cclk			: in		STD_LOGIC;
	Sclk			: inout		STD_LOGIC;
	Din			: out 		STD_LOGIC;
	Dout			: in 		STD_LOGIC;
	AD_CHIP2_ENn		: out 		STD_LOGIC;
	RISE_FALL 		: out 		STD_LOGIC;
	CONVERT 	 	: out 		STD_LOGIC;
	OSC_CNTRL 		: out 		STD_LOGIC;
	ADS_RESET		: out 		STD_LOGIC;	
	BUSY			: in 		STD_LOGIC;
	
	BUSY_TEST		: out 		STD_LOGIC;

	LED1_SEL		: out 		STD_LOGIC;
	LED2_SEL		: out 		STD_LOGIC;
	LED3_SEL		: out 		STD_LOGIC;
	LED4_SEL		: out 		STD_LOGIC

	  );


	END COMPONENT;

-- ********************* SIGNAL DECLARATIONS ************************
--*******************************************************************
signal SP_CS0n	 		: STD_LOGIC;
signal SP_CS1n   		: STD_LOGIC;
signal SP_WEn  			: STD_LOGIC;
signal SP_OEn			: STD_LOGIC;
signal SP_D			: STD_LOGIC_VECTOR(15 DOWNTO 0);
signal SP_A			: STD_LOGIC_VECTOR(23 DOWNTO 1);
signal SP_A_0 			: STD_LOGIC;
signal CHIP3_EN			: std_logic;
signal A			: STD_LOGIC_VECTOR(22 DOWNTO 0);
signal D			: STD_LOGIC_VECTOR(15 DOWNTO 0);
signal FLASH_CS0n		: STD_LOGIC;
signal FLASH_WR_PROTECT		: STD_LOGIC;
signal SRAM_CHIP1_ENn		: STD_LOGIC;
signal OEn				: STD_LOGIC;
signal RWn			: STD_LOGIC;
signal SRAM_UPPER_BYTEn		: STD_LOGIC;
signal SRAM_LOW_BYTEn		: STD_LOGIC;

signal IO13			: std_logic;

signal Cclk			: std_logic;
signal Sclk			: std_logic;
signal Din			: std_logic;
signal Dout			: std_logic;
signal AD_CHIP2_ENn		: std_logic;

signal RISE_FALL 		: STD_LOGIC;
signal CONVERT	 		: STD_LOGIC;
signal OSC_CNTRL 		: STD_LOGIC;


signal ADS_RESET		: STD_LOGIC;	
signal BUSY			: STD_LOGIC := '0';
signal BUSY_TEST		: STD_LOGIC;


signal led1_sel			: STD_LOGIC;
signal led2_sel			: STD_LOGIC;
signal led3_sel			: STD_LOGIC;
signal led4_sel			: STD_LOGIC;


BEGIN

-- Component Instantiation
TOP_TEST : TOP_LEVEL
PORT MAP(

	 SP_CS0n	 	=>		 SP_CS0n,
	 SP_CS1n   		=>		 SP_CS1n,
	 SP_WEn  		=>		 SP_WEn,
	 SP_OEn			=>		 SP_OEn,
	 SP_D			=>		 SP_D,
	 SP_A			=>		 SP_A,
	 SP_A_0 		=>		 SP_A_0,
	 CHIP3_EN		=>		 CHIP3_EN,
	 A			=>		 A,
	 D			=>		 D,
	 FLASH_CS0n		=>		 FLASH_CS0n,
	 FLASH_WR_PROTECT	=>		 FLASH_WR_PROTECT,
	 SRAM_CS1n		=>		 SRAM_CHIP1_ENn,
	 OEn			=>		 OEn,
	 RWn			=>		 RWn,
	 SRAM_UPPER_BYTEn	=>		 SRAM_UPPER_BYTEn,
	 SRAM_LOW_BYTEn		=>		 SRAM_LOW_BYTEn,
	 Cclk			=>		 Cclk,
	 Sclk			=>		 Sclk,
	 Din			=>		 Din,
	 Dout			=>		 Dout,
	 AD_CHIP2_ENn		=>		 AD_CHIP2_ENn,
	 RISE_FALL 		=>		 RISE_FALL,
	 CONVERT	 	=>		 CONVERT,
	 OSC_CNTRL 		=>		 OSC_CNTRL,
	 ADS_RESET		=>		 ADS_RESET,
	 BUSY			=>     BUSY,
	 BUSY_TEST		=>		 BUSY_TEST,

	 IO13			=> 	IO13,

	 led1_sel		=>  	 led1_sel,
	 led2_sel		=>	 led2_sel,
	 led3_sel		=>	 led3_sel,
	 led4_sel		=>	 led4_sel
	);



GEN_CLKS:process
begin
cclk <= '0';
wait for 15 uS;
loop
	cclk <= '1';
	wait for HALFCLKPERIOD;

	cclk <= '0';
	wait for HALFCLKPERIOD;

end loop;
end process GEN_CLKS;


FLOW: process
begin

	dout <= '1';
	SP_A <= "00000000000000000011111";
	SP_CS0n <= '1';
	SP_CS1n <= '1';
	SP_WEn <= '1';
	SP_OEn <= '1';
	wait for 100 us;

	SP_CS1n <= '0';
	SP_WEn <= '0';
	sp_d <= "1111111111111111";
	wait for 100 us;
	
	SP_WEn <= '1';		
	wait for 100 us;
	
	SP_WEn <= '0';
	sp_d<="0000000000000000";
	wait for 100 us;
	
	SP_WEn <= '1';
	wait;
	
		
end process FLOW;



END BEHAVE;