adc_interface.vhd

Serial ADC Interface write in VHDL based on xilinx cpld

					shift8_data_ld <= DM_SNG_LN0;
					dm_num_com <= DM_SNG_LN0(2 downto 0);
					
					if (addr_set = '0') then
						sram_address_com <= SRAM_OFFSET0;						
					end if;
				
				elsif (dm_sng_ln1_flag) then
					shift8_data_ld <= DM_SNG_LN1;
					dm_num_com <= DM_SNG_LN1(2 downto 0);
					
					if (addr_set = '0') then
						sram_address_com <= SRAM_OFFSET1;						
					end if;
					
				elsif (dm_sng_ln2_flag) then
					shift8_data_ld <= DM_SNG_LN2;
					dm_num_com <= DM_SNG_LN2(2 downto 0);
					
					if (addr_set = '0') then
						sram_address_com <= SRAM_OFFSET2;						
					end if;
					
				elsif (dm_sng_ln3_flag) then
					shift8_data_ld <= DM_SNG_LN3;
					dm_num_com <= DM_SNG_LN3(2 downto 0);
					
					if (addr_set = '0') then
						sram_address_com <= SRAM_OFFSET3;						
					end if;
					
				elsif (dm_sng_ln4_flag) then
					shift8_data_ld <= DM_SNG_LN4;
					dm_num_com <= DM_SNG_LN4(2 downto 0);
										
					if (addr_set = '0') then
						sram_address_com <= SRAM_OFFSET4;						
					end if;
					
				elsif (dm_sng_ln5_flag) then
					shift8_data_ld <= DM_SNG_LN5;
					dm_num_com <= DM_SNG_LN5(2 downto 0);
					
					if (addr_set = '0') then
						sram_address_com <= SRAM_OFFSET5;						
					end if;
					
				elsif (dm_sng_ln6_flag) then
					shift8_data_ld <= DM_SNG_LN6;
					dm_num_com <= DM_SNG_LN6(2 downto 0);
					
					if (addr_set = '0') then
						sram_address_com <= SRAM_OFFSET6;						
					end if;
					
				elsif (dm_sng_ln7_flag) then
					shift8_data_ld <= DM_SNG_LN7;
					dm_num_com <= DM_SNG_LN7(2 downto 0);
					
					if (addr_set = '0') then
						sram_address_com <= SRAM_OFFSET7;						
					end if;
								
				end if;			
				
				
				-- Check if ADC inputs remain to be read
				if (dm_sng_ln0_flag or dm_sng_ln1_flag or dm_sng_ln2_flag or
					dm_sng_ln3_flag or dm_sng_ln4_flag or dm_sng_ln5_flag or
					dm_sng_ln6_flag or dm_sng_ln7_flag) then
				
					-- Assert go_shift signal to start din output shift
					go_shift <= '1';
				
					addr_set_com <= '1';					
					main_nxt_state <= WAIT_DM;	
				
				else
					main_nxt_state <= DONE;
				
				end if;
					
					
			---------------------- WAIT_DM State -----------------------
			when WAIT_DM =>
						
				shiftreg_reset <= '0';
			
				-- Wait for shifting to complete
				if (shift_done = '1') then
					main_nxt_state <= ASSIGN_DATA;
				else
					main_nxt_state <= WAIT_DM;			
				
				end if;
				
				
			------------------- ASSIGN_DATA State -----------------------
			when ASSIGN_DATA =>
			
				-- Allow dout data shift into 16-bit input register
				
				-- Set mode flag for operating in direct mode
				mode_flag <= '1';
				
				-- Assert go_shift signal to start shift of data in
				-- Shift SM controls SClk
				go_shift <= '1';
								
				main_nxt_state <= READ_DATA;
			
			------------------- READ_DATA State -----------------------
			when READ_DATA =>
						
				-- Set mode flag for operating in direct mode
				mode_flag <= '1';
						
				shift_en <= '1';
							
				-- Wait for shifting in conversion to complete
				if (shift_done = '1') then							
							
					case dm_num is
					
						--------------- SINGLE ENDED CHANNEL 0 ---------
						when "000" =>	
						
							-- Check if done with number of conversions
							if (SM_ADDRESS = SRAM_HIGH0) then
								
								-- Enable write to SRAM
								statemachine_sram_enn <= '0';						
								statemachine_we <= '0';								
								
								-- Set flag to false
								addr_set_com <= '0';
								dm_sng_ln0_flag_com <= FALSE;
								main_nxt_state <= DIRECT_MODE;
								
							else
								-- Increment counter and continue
								-- conversion cycles						
								count_flag <= '1';
								
								sram_address_com <= SM_ADDRESS + 1;
								
								-- Enable write to SRAM
								statemachine_sram_enn <= '0';						
								statemachine_we <= '0';
								
								main_nxt_state <= DIRECT_MODE;
								
							end if;	
												
											
						-------------- SINGLE ENDED CHANNEL 1 ----------
						when "001" =>	
						
							-- Check if done with number of conversions
							if (SM_ADDRESS = SRAM_HIGH1) then
								
								-- Enable write to SRAM
								statemachine_sram_enn <= '0';	
								statemachine_we <= '0';		
								
								-- Set flag to false
								addr_set_com <= '0';
								dm_sng_ln1_flag_com <= FALSE;
								main_nxt_state <= DIRECT_MODE;
								
							else
								-- Increment counter and continue
								-- conversion cycles						
								count_flag <= '1';
								
								sram_address_com <= SM_ADDRESS + 1;
								
								-- Enable write to SRAM
								statemachine_sram_enn <= '0';						
								statemachine_we <= '0';
								
								main_nxt_state <= DIRECT_MODE;
								
							end if;
						
						
						---------------- SINGLE ENDED CHANNEL 2 -----------
						when "010" =>	
						
							-- Check if done with number of conversions
							if (SM_ADDRESS = SRAM_HIGH2) then
								
								-- Enable write to SRAM
								statemachine_sram_enn <= '0';	
								statemachine_we <= '0';		
								
								-- Set flag to false
								addr_set_com <= '0';
								dm_sng_ln2_flag_com <= FALSE;
								main_nxt_state <= DIRECT_MODE;
								
							else
								-- Increment counter and continue
								-- conversion cycles						
								count_flag <= '1';
								
								sram_address_com <= SM_ADDRESS + 1;
								
								-- Enable write to SRAM
								statemachine_sram_enn <= '0';						
								statemachine_we <= '0';
								
								main_nxt_state <= DIRECT_MODE;
								
							end if;	
						
						
						---------------- SINGLE ENDED CHANNEL 3 -----------
						when "011" =>	
						
							-- Check if done with number of conversions
							if (SM_ADDRESS = SRAM_HIGH3) then
								
								-- Enable write to SRAM								
								statemachine_sram_enn <= '0';	
								statemachine_we <= '0';		
								
								-- Set flag to false
								addr_set_com <= '0';
								dm_sng_ln3_flag_com <= FALSE;
								main_nxt_state <= DIRECT_MODE;
								
							else
								-- Increment counter and continue
								-- conversion cycles						
								count_flag <= '1';
								
								sram_address_com <= SM_ADDRESS + 1;
								
								-- Enable write to SRAM
								statemachine_sram_enn <= '0';						
								statemachine_we <= '0';
								
								main_nxt_state <= DIRECT_MODE;
								
							end if;	

						---------------- SINGLE ENDED CHANNEL 4 -----------
						when "100" =>	
						
							-- Check if done with number of conversions
							if (SM_ADDRESS = SRAM_HIGH4) then
								
								-- Set flag to false
								addr_set_com <= '0';
								dm_sng_ln4_flag_com <= FALSE;
								main_nxt_state <= DIRECT_MODE;
								
							else
								-- Increment counter and continue
								-- conversion cycles						
								count_flag <= '1';
								
								sram_address_com <= SM_ADDRESS + 1;
								
								-- Enable write to SRAM
								statemachine_sram_enn <= '0';						
								statemachine_we <= '0';
								
								main_nxt_state <= DIRECT_MODE;
								
							end if;	
							
							
							
						---------------- SINGLE ENDED CHANNEL 5 -----------
						when "101" =>	
						
							-- Check if done with number of conversions
							if (SM_ADDRESS = SRAM_HIGH5) then
								
								-- Set flag to false
								addr_set_com <= '0';
								dm_sng_ln5_flag_com <= FALSE;
								main_nxt_state <= DIRECT_MODE;
								
							else
								-- Increment counter and continue
								-- conversion cycles						
								count_flag <= '1';
								
								sram_address_com <= SM_ADDRESS + 1;
								
								-- Enable write to SRAM
								statemachine_sram_enn <= '0';						
								statemachine_we <= '0';
								
								main_nxt_state <= DIRECT_MODE;
								
							end if;	
							
							
						---------------- SINGLE ENDED CHANNEL 6 -----------
						when "110" =>	
						
							-- Check if done with number of conversions
							if (SM_ADDRESS = SRAM_HIGH6) then
								
								-- Set flag to false
								addr_set_com <= '0';
								dm_sng_ln6_flag_com <= FALSE;
								main_nxt_state <= DIRECT_MODE;
								
							else
								-- Increment counter and continue
								-- conversion cycles						
								count_flag <= '1';
								
								sram_address_com <= SM_ADDRESS + 1;
								
								-- Enable write to SRAM
								statemachine_sram_enn <= '0';						
								statemachine_we <= '0';
								
								main_nxt_state <= DIRECT_MODE;
								
							end if;	
							
							
						---------------- SINGLE ENDED CHANNEL 7 -----------
						when "111" =>	
						
							-- Check if done with number of conversions
							if (SM_ADDRESS = SRAM_HIGH7) then
								
								-- Set flag to false
								addr_set_com <= '0';
								dm_sng_ln7_flag_com <= FALSE;
								main_nxt_state <= DIRECT_MODE;
								
							else
								-- Increment counter and continue
								-- conversion cycles						
								count_flag <= '1';
								
								sram_address_com <= SM_ADDRESS + 1;
								
								-- Enable write to SRAM
								statemachine_sram_enn <= '0';						
								statemachine_we <= '0';
								
								main_nxt_state <= DIRECT_MODE;
								
							end if;	
					
						when others =>  
							main_nxt_state <= DONE;
						
					end case;
							
						
				else
					main_nxt_state <= READ_DATA;
					
				end if;
				
				
			------------------- DONE State -----------------------
			when DONE =>
			
				main_nxt_state <= DONE;
				
				
			----------------------- DEFAULT State -------------------
			when others =>
			
				main_nxt_state <= IDLE;
				


		end case;  


	end process MAIN_COMB;


end BEHAVE;