adc_interface.vhd

Serial ADC Interface write in VHDL based on xilinx cpld

	-- Needs work:
	-- Seperate process should have timing control when ADC logic writes SRAM
	-- and when Handspring can read SRAM
	-- Statemachine has control to write
	statemachine_oe <= '1';  --Leave OE = '1'
	
	busy_test <= busy;
	RISE_FALL <= '1';
	CONVERT   <= '0';
	OSC_CNTRL <= '1';

	cnt_data_ld <= "00000";
	
	-- Output AD_CHIP2_ENn
	with shift_curr_state select shift_idle <= '1' when IDLE, '0' when others;	
	with main_curr_state select main_wr_addr <= '1' when WRITE_ADDR, '0' when others;
	AD_CHIP2_ENn <= shift_idle and main_wr_addr;		

	with shift_curr_state select SClk <= '1' when SC1, '0' when others;	
	with main_curr_state select ADS_Reset <= '0' when IDLE, '1' when others;
		
	with main_curr_state select SM_WE <= '0' when DONE, '1' when others;	
	with main_curr_state select Mux_Sel <= '0' when DONE, '1' when others;	
			

	
	-- ************************** Process: SEQ ******************************
	-- Purpose:  	Synchronize target state machine
	-- Components: 	none
	SEQ: process(CClk, reset_button) 
	begin	
		if reset_button = '0' then
			main_curr_state <= IDLE;
			shift_curr_state <= IDLE;
			wr_reg_num <= (others => '0');
			
			-- Initialize register write flags
			wr_addr3_flag  <= WR_ADDR3_EN;
			wr_addr4_flag  <= WR_ADDR4_EN;
			wr_addr5_flag  <= WR_ADDR5_EN;
			wr_addr6_flag  <= WR_ADDR6_EN;
			wr_addr7_flag  <= WR_ADDR7_EN;
			wr_addr24_flag <= WR_ADDR24_EN;		
			
			-- Initialize sm_address
			SM_ADDRESS <= (others => '0');
			
			-- Initialize direct mode conversion flags
			dm_num <= (others => '0');
			
			dm_sng_ln0_flag <= DM_SNG_LN0_EN;
			dm_sng_ln1_flag <= DM_SNG_LN1_EN;
			dm_sng_ln2_flag <= DM_SNG_LN2_EN;
			dm_sng_ln3_flag <= DM_SNG_LN3_EN;
			dm_sng_ln4_flag <= DM_SNG_LN4_EN;
			dm_sng_ln5_flag <= DM_SNG_LN5_EN;
			dm_sng_ln6_flag <= DM_SNG_LN6_EN;
			dm_sng_ln7_flag <= DM_SNG_LN7_EN;
			
			addr_set <= '0';

			
		elsif rising_edge(CClk) then
			main_curr_state <= main_nxt_state;
			shift_curr_state <= shift_nxt_state;
			
			-- Register state of address flags
			wr_reg_num <= wr_reg_num_com;			
			wr_addr3_flag  <= wr_addr3_flag_com;
			wr_addr4_flag  <= wr_addr4_flag_com;
			wr_addr5_flag  <= wr_addr5_flag_com;
			wr_addr6_flag  <= wr_addr6_flag_com;
			wr_addr7_flag  <= wr_addr7_flag_com;
			wr_addr24_flag <= wr_addr24_flag_com;
			
			-- Register output sm_address value
			SM_ADDRESS <= sram_address_com;
			
			-- Register state of direct mode conversion flags
			dm_num <= dm_num_com;
			dm_sng_ln0_flag <= dm_sng_ln0_flag_com;
			dm_sng_ln1_flag <= dm_sng_ln1_flag_com;
			dm_sng_ln2_flag <= dm_sng_ln2_flag_com;
			dm_sng_ln3_flag <= dm_sng_ln3_flag_com;
			dm_sng_ln4_flag <= dm_sng_ln4_flag_com;
			dm_sng_ln5_flag <= dm_sng_ln5_flag_com;
			dm_sng_ln6_flag <= dm_sng_ln6_flag_com;
			dm_sng_ln7_flag <= dm_sng_ln7_flag_com;
			
			addr_set <= addr_set_com;
			
		end if;
		
	end process;



	-- ************************ Process: SHIFT_COMB **************************
	-- Purpose:	Shift process controls SClk to ADC.  Shift process controls
	--		when data is being shifted out on Din in either a register
	--		write or sending a direct mode instruction.  The state machine
	--		in these cases will count for an 8 bit shift.
	--		This state machine is also used for counting the number of data
	--		bits on Dout when bring in the 16-bit conversion result.  This
	--		stage is indicated by mode_flag = '1';
	-- Components:	none
	
	SHIFT_COMB: process (shift_curr_state, go_shift, cnt_data_out)
	begin
	
		shift_nxt_state <= shift_curr_state;
		shift8_din_en <= '0';
		cnt_en <= '0';
		shift_done <= '0';	-- Only assert shift_done in SC1 state
		cnt_clr <= '1';		-- Only clear counter in IDLE state
		cnt_ld <= '0';  	-- Never loading counter
		
		case shift_curr_state is

			------------------- IDLE State --------------------------
			when IDLE =>

				if (go_shift = '0') then
					shift_nxt_state <= IDLE; 
				elsif (go_shift = '1') then
					shift_nxt_state <= SC0;
				end if;
				
				cnt_clr <= '0';


			------------------- SC0 State -----------------------
			when SC0 =>
			
				-- If in direct mode, mode_flag = 0
				if (mode_flag = '0') then
				
					-- Enable data shift register
					shift8_din_en <= '1';
						
				end if;
			
				shift_nxt_state <= SC1;				
				

			------------------- SC1 State -----------------------
			when SC1 =>

				cnt_en <= '1';
					
				-- If in register mode - check for count = 8
				if (mode_flag = '0') then
				
					if (cnt_data_out = "01000") then
				
						-- Assert shift_done to main state machine
						shift_done <= '1';
						shift_nxt_state <= IDLE;
					
					else
						shift_nxt_state <= SC0;
					
					end if;		
				
				-- If in direct mode - check for count = 16
				elsif (mode_flag = '1') then
				
					if (cnt_data_out = "10000") then
					
						-- Assert shift_done to main state machine
						shift_done <= '1';
						shift_nxt_state <= IDLE;
					
					else
						shift_nxt_state <= SC0;
					
					end if;	
				
				end if;
				
			
			----------------------- DEFAULT State -------------------
			when others =>
				shift_nxt_state <= IDLE;


		end case;  


	end process SHIFT_COMB;


	-- ************************ Process: MAIN_COMB **************************
	-- Purpose:	Main high level state machine.  This state machine controls
	--		the execution of setting up the registers in the ADC.  This
	--		state machine also controls sending a direct mode instruction
	--		and waiting for the conversion result. 
	--		This state machine is also responsbile for the pointer for 
	--		writing data to SRAM.  Increments sm_address_com.
	-- Components:	none
	
	MAIN_COMB: process (main_curr_state, shift_done)
	begin
	
		main_nxt_state <= main_curr_state;
		shift_en <= '0';
		shift8_ld <= '0';
		mode_flag <= '0';
		shiftreg_reset <= '1';
		count_flag <= '0';	-- Counter for incoming 16-bit data conversions
		shift8_data_ld <= (others => '0');
		go_shift <= '0';	-- Disable shift out data on din
		
		wr_reg_num_com <= wr_reg_num;
		
		-- Default state for register write flags - previous state
		wr_addr3_flag_com <= wr_addr3_flag;
		wr_addr4_flag_com <= wr_addr4_flag;
		wr_addr5_flag_com <= wr_addr5_flag;
		wr_addr6_flag_com <= wr_addr6_flag;
		wr_addr7_flag_com <= wr_addr7_flag;
		wr_addr24_flag_com <= wr_addr24_flag;		
		
		statemachine_sram_enn <= '1';						
		statemachine_we <= '1';
		
		sram_address_com <= SM_ADDRESS;
		
		-- Default state for direct mode conversion flags - previous state
		dm_sng_ln0_flag_com <= dm_sng_ln0_flag;
		dm_sng_ln1_flag_com <= dm_sng_ln1_flag;
		dm_sng_ln2_flag_com <= dm_sng_ln2_flag;
		dm_sng_ln3_flag_com <= dm_sng_ln3_flag;
		dm_sng_ln4_flag_com <= dm_sng_ln4_flag;
		dm_sng_ln5_flag_com <= dm_sng_ln5_flag;
		dm_sng_ln6_flag_com <= dm_sng_ln6_flag;
		dm_sng_ln7_flag_com <= dm_sng_ln7_flag;
		
		dm_num_com <= dm_num;
		
		addr_set_com <= addr_set;
		
		case main_curr_state is

			
			------------------- IDLE State -----------------------
			when IDLE =>			
			
				-- Set initial flag conditions
				wr_addr3_flag_com  <= WR_ADDR3_EN;
				wr_addr4_flag_com  <= WR_ADDR4_EN;
				wr_addr5_flag_com  <= WR_ADDR5_EN;
				wr_addr6_flag_com  <= WR_ADDR6_EN;
				wr_addr7_flag_com  <= WR_ADDR7_EN;
				wr_addr24_flag_com <= WR_ADDR24_EN;
				
				dm_sng_ln0_flag_com <= DM_SNG_LN0_EN;
				dm_sng_ln1_flag_com <= DM_SNG_LN1_EN;
				dm_sng_ln2_flag_com <= DM_SNG_LN2_EN;
				dm_sng_ln3_flag_com <= DM_SNG_LN3_EN;
				dm_sng_ln4_flag_com <= DM_SNG_LN4_EN;
				dm_sng_ln5_flag_com <= DM_SNG_LN5_EN;
				dm_sng_ln6_flag_com <= DM_SNG_LN6_EN;
				dm_sng_ln7_flag_com <= DM_SNG_LN7_EN;				
				
				addr_set_com <= '0';
				
				main_nxt_state <= WRITE_ADDR;				
				
			
			------------------- WRITE_ADDR State -----------------------
			when WRITE_ADDR =>
			
				-- Control to load data shift register
				shift8_ld <= '1';
				
				-- Check which register to write
				-- On each consecutive loop, write to new register
				-- Set flag of current write to false for consecutive loops
				-- Load shift8 parallel data value, shift8_data_ld
						
				if (wr_addr3_flag) then
					shift8_data_ld <= ADDR3;
					wr_addr3_flag_com <= FALSE;
					wr_reg_num_com <= "011";

				elsif (wr_addr7_flag) then
					shift8_data_ld <= ADDR7;
					wr_addr7_flag_com <= FALSE;
					wr_reg_num_com <= "111";

				elsif (wr_addr4_flag) then
					shift8_data_ld <= ADDR4;
					wr_addr4_flag_com <= FALSE;
					wr_reg_num_com <= "100";

				elsif (wr_addr5_flag) then
					shift8_data_ld <= ADDR5;
					wr_addr5_flag_com <= FALSE;
					wr_reg_num_com <= "101";

				elsif (wr_addr6_flag) then
					shift8_data_ld <= ADDR6;
					wr_addr6_flag_com <= FALSE;
					wr_reg_num_com <= "110";

				elsif (wr_addr24_flag) then
					shift8_data_ld <= ADDR24;
					wr_addr24_flag_com <= FALSE;
					wr_reg_num_com <= "000";

				end if;
											
				-- Assert go_shift signal to start din output shift
				go_shift <= '1';				
				main_nxt_state <= WAIT_ADDR;		
				
				
			------------------- WRITE_ADDR State -----------------------
			when WAIT_ADDR =>
						
				-- Wait for shifting to complete
				if (shift_done = '1') then
					main_nxt_state <= ADDR_DATA;
				else
					main_nxt_state <= WAIT_ADDR;			
				
				end if;

			------------------- ADDR_DATA State -----------------------
			when ADDR_DATA =>

				-- Control to load data shift register
				shift8_ld <= '1';
				
				-- Load data shift register with data for register
				-- write
				case wr_reg_num is
					when "011" =>	shift8_data_ld <= DATA_WR_ADDR3;
					when "111" =>	shift8_data_ld <= DATA_WR_ADDR7;
					when "100" =>	shift8_data_ld <= DATA_WR_ADDR4;
					when "101" =>	shift8_data_ld <= DATA_WR_ADDR5;
					when "110" =>	shift8_data_ld <= DATA_WR_ADDR6;
					when "000" =>	shift8_data_ld <= DATA_WR_ADDR24;
					when others =>  shift8_data_ld <= "11111111";
				end case;
					
				-- Assert go_shift signal to start din output shift
				go_shift <= '1';
								
				main_nxt_state <= WAIT_DATA;	
				
			
			------------------- WRITE_ADDR State -----------------------
			when WAIT_DATA =>

				-- Wait for shifting to complete
				if (shift_done = '1') then
					
					-- Check if registers remain to write
					if ( wr_addr3_flag or wr_addr7_flag or
					     wr_addr4_flag or wr_addr5_flag or
					     wr_addr6_flag or wr_addr24_flag ) then
						main_nxt_state <= WRITE_ADDR;
					
					else 
						main_nxt_state <= DIRECT_MODE;
						
					end if;
					
				else	
					-- Wait for current data write to complete
					main_nxt_state <= WAIT_DATA;			
				
				end if;
				
			------------------- DIRECT_MODE State -----------------------
			when DIRECT_MODE =>
											
				-- Control to load data shift register
				shift8_ld <= '1';
										
				-- Assign Din to ADC to be direct mode command
				-- Check which direct mode channel to read
				-- Load shift8 parallel data value, shift8_data_ld
				-- Also load sm_address_com with designated memory space
				-- for data from the specific input channel
			
				if (dm_sng_ln0_flag) then