📄 adc_interface.vhd
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-- **************************************************************
--
-- Owner: Xilinx Inc.
-- File: adc_interface.vhd
--
-- Purpose: Code to configure ADS7870. This code will initiate multiple conversions
-- using ReadBack Mode 1.
-- Does the following:
--
-- 1) Writes 00001000 to ADDR3. This specifies ReadBack Mode 2
-- 2) Writes 00001111 to ADDR6. This specifies I/O 4,3,2,1 are outputs
-- 3) Writes 00001111 to ADDR5. This causes all 4 I/O to output '0101'
-- 4) Writes 00111100 to ADDR7. This turns on Internal Vref
-- 5) Loops and performs multiple conversions after these registers are set up
--
--
-- **************************************************************
LIBRARY IEEE;
USE ieee.STD_LOGIC_1164.all;
USE ieee.STD_LOGIC_arith.all;
USE ieee.STD_LOGIC_unsigned.all;
entity ADC_INTERFACE is
port(
--ADS7870 Signals
Cclk : in STD_LOGIC;
Sclk : inout STD_LOGIC;
Din : out STD_LOGIC;
Dout : in STD_LOGIC;
AD_CHIP2_ENn : out STD_LOGIC;
busy : in STD_LOGIC;
busy_test : out STD_LOGIC;
ADS_reset : out STD_LOGIC;
RISE_FALL : out STD_LOGIC;
CONVERT : out STD_LOGIC;
OSC_CNTRL : out STD_LOGIC;
-- Miscellaneous Signals
ADC_DATA : out STD_LOGIC_vector(15 downto 0);
Reset_Button : in STD_LOGIC;
-- StateMachine Specific Signals
Mux_Sel : out STD_LOGIC;
statemachine_sram_enn : inout STD_LOGIC;
statemachine_we : inout STD_LOGIC;
statemachine_oe : out STD_LOGIC;
SM_ADDRESS : inout STD_LOGIC_VECTOR(22 DOWNTO 0);
SM_WE : out STD_LOGIC
);
end ADC_INTERFACE;
architecture BEHAVE of ADC_INTERFACE is
-- ********************** CONSTANT DECLARATIONS *******************************
--********************* ADDR0 (ADC OUTPUT REGISTER) ****************
-- Description: ADDR0 stores the LS Byte of the conversion result.
-- R/W : READ ONLY
constant RD_ADDR0_EN : BOOLEAN := FALSE;
constant ADDR0 : STD_LOGIC_VECTOR(7 downto 0) := "01000000"; -- Read ADDR 0
--********************* ADDR1 (ADC OUTPUT REGISTER) ****************
-- Description: ADDR1 stores the MS Byte of the converstion result
-- R/W : READ ONLY
constant RD_ADDR1_EN : BOOLEAN := FALSE;
constant ADDR1 : STD_LOGIC_VECTOR(7 downto 0) := "01000001"; -- Read ADDR 1
--********************* ADDR2 (PGA VALID REGISTER) ****************
-- Description: ADDR2 reveals if PGA has exceeded allowable values
-- R/W : READ ONLY
constant RD_ADDR2_EN : BOOLEAN := FALSE;
constant ADDR2 : STD_LOGIC_VECTOR(7 downto 0) := "01000010"; -- Read ADDR2
--********************* ADDR3 (A/D CONTROL REGISTER) ****************
-- Description: ADDR3 configures the CCLK Divider and read back mode operation
-- R/W : R/W
constant WR_ADDR3_EN : BOOLEAN := TRUE;
constant ADDR3 : STD_LOGIC_VECTOR(7 downto 0) := "00000011"; -- Write/Read to Control Register
constant DATA_WR_ADDR3 : STD_LOGIC_VECTOR(7 downto 0) := "00000100"; -- Data to be written
--********************* ADDR4 (GAIN/MUX REGISTER) ****************
-- Description: ADDR4 configures the PGA gain and the input channel selection.
-- (A direct mode operation will accomplish this as well)
-- R/W : R/W
constant WR_ADDR4_EN : BOOLEAN := FALSE;
constant ADDR4 : STD_LOGIC_VECTOR(7 downto 0) := "00000100"; -- Write/Read to Gain/Mux Register
constant DATA_WR_ADDR4 : STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- Data to be written
--********************* ADDR5 (DIGITAL I/O STATE REGISTER) ****************
-- Description: ADDR5 sets/reveals the state of the digital IO pins.
-- R/W : R/W
constant WR_ADDR5_EN : BOOLEAN := TRUE;
constant ADDR5 : STD_LOGIC_VECTOR(7 downto 0) := "00000101"; -- Write/Read Digital I/O State Reg
constant DATA_WR_ADDR5 : STD_LOGIC_VECTOR(7 downto 0) := "00000101"; -- Data to be written
--********************* ADDR6 (DIGITAL I/O CONTROL REGISTER) ****************
-- Description: ADDR6 determines whether each of the four IO pins will be an output or and output
-- R/W : R/W
constant WR_ADDR6_EN : BOOLEAN := TRUE;
constant ADDR6 : STD_LOGIC_VECTOR(7 downto 0) := "00000110";
constant DATA_WR_ADDR6 : STD_LOGIC_VECTOR(7 downto 0) := "00001111";
--********************* ADDR7 (REF/OSCILLATOR CONTROL REGISTER)**************
-- Description: ADDR7 determines:
-- a) Whether the internal oscillator is used for the conversion clock
-- b) Whether the internal voltage reference and buffer are ON or OFF
-- c) Whether the voltage reference is 2.5V, 2.048V or 1.15V
-- R/W : R/W
constant WR_ADDR7_EN : BOOLEAN := TRUE;
constant ADDR7 : STD_LOGIC_VECTOR(7 downto 0) := "00000111";
constant DATA_WR_ADDR7 : STD_LOGIC_VECTOR(7 downto 0) := "00111100";
--********************* ADDR24 (SERIAL INTERFACE CONTROL REGISTER) **********
-- Description: ADDR24 allows certain aspects of the serial interface to be changed by the user
-- R/W : R/W
constant WR_ADDR24_EN : BOOLEAN := FALSE;
constant ADDR24 : STD_LOGIC_VECTOR(7 downto 0) := "00011000"; -- Serial Interface Control
constant DATA_WR_ADDR24 : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
--********************* ADDR31 (ID REGISTER) ******************************
-- Description: ADDR31 reveals which version of ADS7870 is being used
-- R/W : READ ONLY
constant WR_ADDR31_EN : BOOLEAN := FALSE;
constant ADDR31 : STD_LOGIC_VECTOR(7 downto 0) := "00011111"; -- ID Register
-- *************** DIRECT MODE CONVERSION SINGLE ENDED CHANNEL 0 ********************
constant DM_SNG_LN0_EN : BOOLEAN := TRUE;
constant DM_SNG_LN0 : STD_LOGIC_VECTOR(7 downto 0) := "10001000";
constant SRAM_OFFSET0 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000000";
constant SRAM_HIGH0 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000111";
-- *************** DIRECT MODE CONVERSION SINGLE ENDED CHANNEL 1 *********************
constant DM_SNG_LN1_EN : BOOLEAN := TRUE;
constant DM_SNG_LN1 : STD_LOGIC_VECTOR(7 downto 0) := "10001001";
constant SRAM_OFFSET1 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000001000";
constant SRAM_HIGH1 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000001111";
-- *************** DIRECT MODE CONVERSION SINGLE ENDED CHANNEL 2 *********************
constant DM_SNG_LN2_EN : BOOLEAN := TRUE;
constant DM_SNG_LN2 : STD_LOGIC_VECTOR(7 downto 0) := "10001010";
constant SRAM_OFFSET2 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000010000";
constant SRAM_HIGH2 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000010111";
-- *************** DIRECT MODE CONVERSION SINGLE ENDED CHANNEL 3 *********************
constant DM_SNG_LN3_EN : BOOLEAN := FALSE;
constant DM_SNG_LN3 : STD_LOGIC_VECTOR(7 downto 0) := "10001011";
constant SRAM_OFFSET3 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000011000";
constant SRAM_HIGH3 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000011111";
-- *************** DIRECT MODE CONVERSION SINGLE ENDED CHANNEL 4 *********************
constant DM_SNG_LN4_EN : BOOLEAN := FALSE;
constant DM_SNG_LN4 : STD_LOGIC_VECTOR(7 downto 0) := "10001100";
constant SRAM_OFFSET4 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000100000";
constant SRAM_HIGH4 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000100111";
-- *************** DIRECT MODE CONVERSION SINGLE ENDED CHANNEL 5 *********************
constant DM_SNG_LN5_EN : BOOLEAN := FALSE;
constant DM_SNG_LN5 : STD_LOGIC_VECTOR(7 downto 0) := "10001101";
constant SRAM_OFFSET5 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000101000";
constant SRAM_HIGH5 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000101111";
-- *************** DIRECT MODE CONVERSION SINGLE ENDED CHANNEL 6 *********************
constant DM_SNG_LN6_EN : BOOLEAN := TRUE;
constant DM_SNG_LN6 : STD_LOGIC_VECTOR(7 downto 0) := "10001110";
constant SRAM_OFFSET6 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000110000";
constant SRAM_HIGH6 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000110111";
-- *************** DIRECT MODE CONVERSION SINGLE ENDED CHANNEL 7 *********************
constant DM_SNG_LN7_EN : BOOLEAN := TRUE;
constant DM_SNG_LN7 : STD_LOGIC_VECTOR(7 downto 0) := "10001111";
constant SRAM_OFFSET7 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000111000";
constant SRAM_HIGH7 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000111111";
-- ********************** SIGNAL DECLARATIONS *********************************
-- Shift State Machine State Type
type Shift_StateType is ( IDLE, SC0, SC1 );
-- Main State Machine State Type
type Main_StateType is ( IDLE, WRITE_ADDR, WAIT_ADDR, ADDR_DATA, WAIT_DATA,
DIRECT_MODE, WAIT_DM, ASSIGN_DATA, READ_DATA, DONE );
-- Synchronous state machine state identifiers
signal shift_curr_state, shift_nxt_state : Shift_StateType;
signal main_curr_state, main_nxt_state : Main_StateType;
-- Flag for ADC operating mode
-- mode_flag = 0 if operating in register mode
-- mode_flag = 1 if operating in direct mode
signal mode_flag : STD_LOGIC;
-- SRAM address output for writing incoming data to memory
signal sram_address_com : STD_LOGIC_VECTOR (22 downto 0);
-- Start shifting signal from main state machine
signal go_shift : STD_LOGIC;
-- 8-bit shift register signals
signal shift8_clr, shift8_ld, shift8_din_en : STD_LOGIC;
signal shift8_in : STD_LOGIC;
signal shift8_clk : STD_LOGIC;
-- 8-bit data to shift (parallel load)
signal shift8_data_ld : STD_LOGIC_VECTOR (7 downto 0);
-- 8-bit parallel output of shift register (not used)
signal shift8_out_data : STD_LOGIC_VECTOR (7 downto 0);
-- 16-bit shift register signals
signal shiftreg_reset, shift_ld, shift_en: STD_LOGIC;
signal shiftreg_data_in: STD_LOGIC_VECTOR(15 downto 0);
-- 4-bit counter signals
signal cnt_data_ld : STD_LOGIC_VECTOR (4 downto 0);
signal cnt_en : STD_LOGIC;
signal cnt_ld : STD_LOGIC;
signal cnt_clr : STD_LOGIC;
signal cnt_data_out : STD_LOGIC_VECTOR (4 downto 0);
signal shift_done : STD_LOGIC := '0';
-- Flag for writing to each register
signal wr_addr3_flag, wr_addr3_flag_com : BOOLEAN;
signal wr_addr4_flag, wr_addr4_flag_com : BOOLEAN;
signal wr_addr5_flag, wr_addr5_flag_com : BOOLEAN;
signal wr_addr6_flag, wr_addr6_flag_com : BOOLEAN;
signal wr_addr7_flag, wr_addr7_flag_com : BOOLEAN;
signal wr_addr24_flag, wr_addr24_flag_com : BOOLEAN;
signal wr_reg_num, wr_reg_num_com : STD_LOGIC_VECTOR (2 downto 0);
-- Control signals for CS (AD_CHIP2_ENn)
signal shift_idle, main_wr_addr : STD_LOGIC;
-- Counter for incoming ADC 16-bit data conversions
signal count_flag : STD_LOGIC := '0';
-- Flags for multiple inputs on ADC
-- Single ended input channels (LN0 - LN7)
signal dm_sng_ln0_flag, dm_sng_ln0_flag_com : BOOLEAN;
signal dm_sng_ln1_flag, dm_sng_ln1_flag_com : BOOLEAN;
signal dm_sng_ln2_flag, dm_sng_ln2_flag_com : BOOLEAN;
signal dm_sng_ln3_flag, dm_sng_ln3_flag_com : BOOLEAN;
signal dm_sng_ln4_flag, dm_sng_ln4_flag_com : BOOLEAN;
signal dm_sng_ln5_flag, dm_sng_ln5_flag_com : BOOLEAN;
signal dm_sng_ln6_flag, dm_sng_ln6_flag_com : BOOLEAN;
signal dm_sng_ln7_flag, dm_sng_ln7_flag_com : BOOLEAN;
signal dm_num, dm_num_com : STD_LOGIC_VECTOR (2 downto 0);
-- Flags for initializing address pointers for each direct mode conversion
signal addr_set, addr_set_com : STD_LOGIC;
-- ************************ COMPONENT DECLARATIONS *****************************
-- 16-bit shift register with parallel load
component SHIFT16
port(
clk : in STD_LOGIC; -- Clock
clr : in STD_LOGIC; -- Clear
data_ld : in STD_LOGIC; -- Data load enable
data_in : in STD_LOGIC_VECTOR (15 downto 0); -- Data to load in
shift_in : in STD_LOGIC; -- Serial data in
shift_en : in STD_LOGIC; -- Shift enable
data_out : out STD_LOGIC_VECTOR (15 downto 0) -- Shifted data
);
end component;
-- 8-bit shift register will serial data out (MSB first shifting)
component SHIFT8
port(
clk : in STD_LOGIC; -- Clock
clr : in STD_LOGIC; -- Clear
data_ld : in STD_LOGIC; -- Data load enable
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- Data to load in
shift_in : in STD_LOGIC; -- Serial data in
shift_en : in STD_LOGIC; -- Shift enable
shift_out : out STD_LOGIC; -- Shift serial data out
data_out : out STD_LOGIC_VECTOR (7 downto 0) -- Shifted data
);
end component;
-- 5-bit counter for shifting serial data to ADC
component UPCNT5
port(
data : in STD_LOGIC_VECTOR (4 downto 0); -- Serial data in
cnt_en : in STD_LOGIC; -- Count enable
load : in STD_LOGIC; -- Load line enable
clr : in STD_LOGIC; -- Active low clear
clk : in STD_LOGIC; -- Clock
qout : inout STD_LOGIC_VECTOR (4 downto 0)
);
end component;
begin
-- *********************** COMPONENT DEFINITIONS ************************
-- Component: SHIFT_ADC
-- Purpose: 16-bit shift register for data from ADC in twos complement
SHIFT_ADC : SHIFT16
port map(
clk => SClk, -- Clock
clr => shiftreg_reset, -- Clear
data_ld => shift_ld, -- Data load enable
data_in => shiftreg_data_in, -- Data to load in
shift_in => Dout, -- Serial data in
shift_en => shift_en, -- Shift enable
data_out => adc_data); -- Shifted data
-- Component: SHIFT_DATA
-- Purpose: 8-bit shift register to send data to ADC
SHIFT_DATA : SHIFT8
port map(
clk => shift8_clk, -- Clock
clr => shift8_clr, -- Clear
data_ld => shift8_ld, -- Data load enable
data_in => shift8_data_ld, -- Data to load in
shift_in => shift8_in, -- Serial data in
shift_en => shift8_din_en, -- Shift enable
shift_out => Din, -- Data to shift to ADC
data_out => shift8_out_data); -- Shifted data
-- Component: CNT5
-- Purpose: 5-bit counter for shifting serial data to ADC
CNT5 : UPCNT5
port map(
data => cnt_data_ld, -- Parallel data in
cnt_en => cnt_en, -- Count enable
load => cnt_ld, -- Load line enable
clr => cnt_clr, -- Active low clear
clk => Cclk, -- Clock
qout => cnt_data_out); -- Parallel data out
-- *************************** SIGNAL DEFINITIONS **************************
-- Bit stuff data register to ADC with zeros
shift8_in <= '0';
shift8_clr <= '1';
-- Shift out data on falling edge of CClk (before active rising edge of SClk)
shift8_clk <= not (CClk);
-- Default if loading 16-bit ADC data register
shiftreg_data_in <= "0000000000000000";
-- Never loading 16-bit ADC data register, load = '0'
shift_ld <= '0';
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