top_level.vhd

Serial ADC Interface write in VHDL based on xilinx cpld

-- **************************************************************
-- 
-- Owner:	Xilinx Inc.
-- File:  	top_level.vhd
--
-- Purpose:  	This top level file creates the bidirectional buffering
--           	scheme in the XPLA3.  It instantiates the state machine 
--		   	   which sends a bunch of bytes to the ADS7870.  
--
--
-- **************************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;

entity TOP_LEVEL is
	port(
	SP_CS0n	 		: in 	STD_LOGIC;
	SP_CS1n   		: in 	STD_LOGIC;
	SP_WEn  		: in 	STD_LOGIC;
	SP_OEn			: in 	STD_LOGIC;
	SP_D			: inout STD_LOGIC_VECTOR(15 DOWNTO 0);
	SP_A			: in 	STD_LOGIC_VECTOR(23 DOWNTO 1);
	SP_A_0 			: out   STD_LOGIC;
	CHIP3_EN		: out 	STD_LOGIC;
	A			: out 	STD_LOGIC_VECTOR(22 DOWNTO 0);
	D			: inout STD_LOGIC_VECTOR(15 DOWNTO 0);
	FLASH_CS0n		: out 	STD_LOGIC;
	FLASH_WR_PROTECT	: out 	STD_LOGIC;
	SRAM_CS1n		: inout STD_LOGIC;
	OEn			: out 	STD_LOGIC;
	RWn			: out 	STD_LOGIC;

	IO13			: out 	STD_LOGIC;

	SRAM_UPPER_BYTEn	: out 	STD_LOGIC;
	SRAM_LOW_BYTEn		: out 	STD_LOGIC;

	--ADS7870 Signals
	Cclk			: in	STD_LOGIC;
	Sclk			: inout	STD_LOGIC;
	Din			: out 	STD_LOGIC;
	Dout			: in 	STD_LOGIC;
	AD_CHIP2_ENn		: out 	STD_LOGIC;
	RISE_FALL 		: out 	STD_LOGIC;
	CONVERT 	 	: out 	STD_LOGIC;
	OSC_CNTRL 		: out 	STD_LOGIC;
	ADS_RESET		: out 	STD_LOGIC;	
	BUSY			: in 	STD_LOGIC;
	
	BUSY_TEST		: out 	STD_LOGIC;

--	AD_D0			: in 	STD_LOGIC;
--	AD_D1			: in 	STD_LOGIC;
--	AD_D2			: in 	STD_LOGIC;
--	AD_D3			: in 	STD_LOGIC;


--	SRAM_Write_En		: inout	STD_LOGIC;

	LED1_SEL		: out 	STD_LOGIC;
	LED2_SEL		: out 	STD_LOGIC;
	LED3_SEL		: out 	STD_LOGIC;
	LED4_SEL		: out 	STD_LOGIC

	);

end TOP_LEVEL;

architecture BEHAVE of TOP_LEVEL is


constant RESET_ADDR : STD_LOGIC_VECTOR(23 downto 0) := "000000000000000000111110";  -- A1 to A5 asserted 


-- ************************ SIGNAL DECLARATIONS *****************
signal X								: STD_LOGIC;
signal SM_WE						: STD_LOGIC;

signal SRAM_Write_En 			: STD_LOGIC;
signal SRAM_Read_En 				: STD_LOGIC;
signal SRAM_ReADDATA			: STD_LOGIC_VECTOR(15 DOWNTO 0);
signal SRAM_Write_Data			: STD_LOGIC_VECTOR(15 DOWNTO 0);
	
signal StateMachine_SRAM_ENn		: STD_LOGIC;
signal StateMachine_WE			: STD_LOGIC;
signal StateMachine_OE			: STD_LOGIC;

signal MUX_OUT				: STD_LOGIC_VECTOR(15 DOWNTO 0);
signal Mux_Sel				: STD_LOGIC;

signal SM_ADDRESS			: STD_LOGIC_VECTOR(22 DOWNTO 0);

signal ADC_DATA				: STD_LOGIC_VECTOR(15 DOWNTO 0);

signal RESET_BUTTON			: STD_LOGIC;

component ADC_INTERFACE 
	port(
		--ADS7870 Signals 
		Cclk			: 	in	 STD_LOGIC;
		Sclk			: 	inout STD_LOGIC;
		Din			: 	out STD_LOGIC;
		Dout			: 	in  STD_LOGIC;
		AD_CHIP2_ENn		: 	out STD_LOGIC;
		busy				: 	in  STD_LOGIC;
		busy_test		:  out STD_LOGIC;
		ADS_reset		:  out STD_LOGIC;
		RISE_FALL 		:  out STD_LOGIC;
		CONVERT 	 		:  out STD_LOGIC;
		OSC_CNTRL 		:  out STD_LOGIC;

			-- Miscellaneous Signals

		ADC_DATA		:	out STD_LOGIC_VECTOR(15 downto 0);
		Reset_Button		:	in  STD_LOGIC;


			-- StateMachine Specific Signals

		Mux_Sel			:  out STD_LOGIC;
		statemachine_sram_enn	: inout STD_LOGIC;
		statemachine_we		: inout STD_LOGIC;
		statemachine_oe		: out STD_LOGIC;
		SM_ADDRESS		: 	inout STD_LOGIC_VECTOR(22 DOWNTO 0);
		SM_WE			: 	out STD_LOGIC
	     );
	     
end component;


begin


ASSERT_RESET_BUTTON: process(SP_A, SP_D, SP_WEn, SP_CS1n)
begin
	if(SP_CS1n = '0') then
		if(SP_WEn'event and SP_WEn='1') then
		  	if (SP_D = "1111111111111111" and (SP_A & '0') = RESET_ADDR) then
		  		RESET_BUTTON <= '0'; -- reset SM
		  	
		  	elsif (SP_D = "0000000000000000" and (SP_A & '0') = RESET_ADDR) then
		  		RESET_BUTTON<= '1';
		  	
		  	end if;
		end if;
	 end if;
	 
end process ASSERT_RESET_BUTTON;


--
--                                                           SRAM_Write_En
--                                                                  |
--                                            ---------------------|>---
--                                           |                           | 
--                 SRAM_Read_En              |                            ---[]  D
--                       |                   |    SRAM_ReADDATA         |
--                  ----<|-------------------|---------------------<|----
--                 |                         |
--   DATA []--------                         |
--                 |       SRAM_Write_Data   |
--                  ----|>-------------------
--
-- 
--
--



--Create 2:1 Multiplexer
--
--                      |\
--   SRAM_Write_Data   -| |
--                      | |- MUX_OUT
--         ADC_DATA    -| |
--                      |/
--                       |
--                      Mux_Sel

MUX_OUT(15 DOWNTO 0) <= SRAM_Write_Data(15 DOWNTO 0) when Mux_Sel = '0' else
								ADC_DATA;


SRAM_Write_En <= SM_WE or (not SM_WE and ( not SP_WEn and (not SP_CS0n or not SP_CS1n) ) ); -- Enable Signal		




-- Bidirectional Bus, D (Goes TO/FROM the springboard):

D(15 DOWNTO 0) <=  MUX_OUT(15 DOWNTO 0) when (SRAM_Write_En = '1') else (others => 'Z');

SRAM_READDATA(15 DOWNTO 0) <= D(15 DOWNTO 0);


SRAM_Read_En <= not SP_OEn and (not SP_CS0n or not SP_CS1n);  --  Enable Signal

-- Bidirectional Bus, DATA (Goes TO/FROM Handspring Unit):
SP_D(15 DOWNTO 0) <= SRAM_READDATA(15 DOWNTO 0) when (SRAM_Read_En = '1') else (others => 'Z');

SRAM_Write_Data(15 DOWNTO 0) <= SP_D(15 DOWNTO 0);


	
--************************************************************************



--Create 2:1 Multiplexer
--
--                      |\
--	   SP_CS1n     -| |
--                      | |- SRAM_CS1n
--StateMachine_SRAM_Enn-| |
--                      |/
--                       |
--                      Mux_Sel

SRAM_CS1n <= SP_CS1n when Mux_Sel = '0' else
	  StateMachine_SRAM_Enn;


--Create 2:1 Multiplexer
--
--                      |\
--		SP_WEn -| |
--                      | |- RWn
--StateMachine_WE      -| |
--                      |/
--                       |
--                      Mux_Sel

RWn <= SP_WEn when Mux_Sel = '0' else
			  StateMachine_WE;

--Create 2:1 Multiplexer
--
--                      |\
--	      SP_OEn   -| |
--                      | |- OEn
--StateMachine_OE      -| |
--                      |/
--                       |
--                      Mux_Sel

OEn <= SP_OEn when Mux_Sel = '0' else
	  StateMachine_OE;




--Create 2:1 Multiplexer
--
--                      |\
--             SP_A    -| |
--                      | |- A
--       Addr_count    -| |
--                      |/
--                       |
--                      Mux_Sel

A(22 DOWNTO 0) <= SP_A(23 DOWNTO 1) when Mux_Sel = '0' else
			  SM_ADDRESS;

SP_A_0 <= '0';  --  SP_A(0) is not used in this version of Handspring Visor
     


--SRAM Control Signals
SRAM_UPPER_BYTEn	<= '0';
SRAM_LOW_BYTEn		<= '0';

--Flash Control Signals
FLASH_CS0n 	<= '1';
FLASH_WR_PROTECT	<= '1';

--Miscellaneous
CHIP3_EN <= SP_CS1n;    -- Brings CS1 to an outside pin so we can probe it
IO13 		<= SRAM_CS1n;


--LED's
led1_sel <= '1'; --  not AD_D0;  --Turn LEDs on when AD_IO pins are logic high
led2_sel <= '1'; --not AD_D1;
led3_sel <= '1'; --not AD_D2;
led4_sel <= '1'; --not AD_D3;




-- *************************** State Machine Instantiation *******************
ADC : ADC_INTERFACE
  port map(
		--ADS7870 Signals 
		Cclk				=>   Cclk,
		Sclk				=>   Sclk,
		Din				=>   Din,
		Dout				=>   Dout,
		AD_CHIP2_ENn			=>   AD_CHIP2_ENn,
		busy				=>   busy,
		busy_test			=>   busy_test,
		ADS_RESET			=>   ADS_RESET,
		RISE_FALL 			=>   RISE_FALL,
		CONVERT 	 		=>   CONVERT,
		OSC_CNTRL 			=>   OSC_CNTRL,
		ADC_DATA			=>   ADC_DATA,			
		Reset_Button			=>   Reset_Button,

		Mux_Sel				=>   Mux_Sel,
		
		statemachine_sram_enn 		=>  statemachine_sram_enn,
		statemachine_we		  	=>  statemachine_we,
		statemachine_oe		 	=>  statemachine_oe,
		SM_ADDRESS			=>  SM_ADDRESS,
 		SM_WE				=>   SM_WE



		);

END BEHAVE;