adc_interface_tb.vhd

Serial ADC Interface write in VHDL based on xilinx cpld

-- **************************************************************
--
-- Owner:	Xilinx Inc.
-- File:  	adc_interface_tb.vhd
--
-- Purpose: 	Test bench for ADC_INTERFACE entity.  Checks that
--		data is sent to ADC from configure registers.  Simulates
--		Dout from ADC is = '1';
--
-- **************************************************************

library ieee;
use IEEE.std_logic_1164.all;

entity ADC_INTERFACE_TB is 
end ADC_INTERFACE_TB;


architecture BEHAVIOR of ADC_INTERFACE_TB is

-- ********************** CONSTANT DECLARATIONS *********************
constant 	RESET_ACTIVE 		: 	STD_LOGIC := '0';

constant	CLOCK_PERIOD		:	time	:= 400 nS;
constant	HALFCLOCKPERIOD 	:	time	:= 200 nS;
constant	CLOCKSKEW		:	time	:= 5500 pS;
constant	CLK2QDELAY		:	time	:= 5 nS;
constant	CLKOUTDELAY		:	time	:= 3 nS;


-- ************************ SIGNAL DECLARATIONS **********************
signal Cclk	: STD_LOGIC := '0';
signal Sclk 	: STD_LOGIC;
signal Dout	: STD_LOGIC;
signal busy	: STD_LOGIC; 
signal Din, AD_CHIP2_ENn, busy_test, ADS_reset, RISE_FALL, CONVERT, OSC_CNTRL : STD_LOGIC;

signal ADC_DATA			: STD_LOGIC_vector(15 downto 0);
signal Reset_Button		: STD_LOGIC;
signal Mux_Sel			: STD_LOGIC;
signal statemachine_sram_enn	: STD_LOGIC;
signal statemachine_we		: STD_LOGIC;
signal statemachine_oe		: STD_LOGIC;
signal SM_WE			: STD_LOGIC;
signal SM_ADDRESS		: STD_LOGIC_VECTOR(22 DOWNTO 0);


-- ************************* COMPONENT DECLARATIONS ********************

component ADC_INTERFACE
	port(
	
		--ADS7870 Signals 
		Cclk			:  in	 STD_LOGIC;
		Sclk			:  inout STD_LOGIC;
		Din			:  out STD_LOGIC;
		Dout			:  in  STD_LOGIC;
		AD_CHIP2_ENn		:  out STD_LOGIC;
		busy			:  in  STD_LOGIC;
		busy_test		:  out STD_LOGIC;
		ADS_reset		:  out STD_LOGIC;
		RISE_FALL 		:  out STD_LOGIC;
		CONVERT 	 	:  out STD_LOGIC;
		OSC_CNTRL 		:  out STD_LOGIC;

		-- Miscellaneous Signals
		ADC_DATA		:  out STD_LOGIC_vector(15 downto 0);
		Reset_Button		:  in  STD_LOGIC;


		-- StateMachine Specific Signals
		Mux_Sel			:  out STD_LOGIC;
		statemachine_sram_enn	:  inout STD_LOGIC;
		statemachine_we		:  inout STD_LOGIC;
		statemachine_oe		:  out STD_LOGIC;
		SM_ADDRESS		:  inout STD_LOGIC_VECTOR(22 DOWNTO 0);
		SM_WE			:  out STD_LOGIC
		
	   );


end component;

begin

	-- ********************** COMPONENT DEFINITION *****************
	
	SM : ADC_INTERFACE
	port map (
	
		--ADS7870 Signals 
		Cclk			=> Cclk,
		Sclk			=> Sclk,
		Din			=> Din,
		Dout			=> Dout,
		AD_CHIP2_ENn		=> AD_CHIP2_Enn,
		busy			=> busy,
		busy_test		=> busy_test,
		ADS_reset		=> ADS_reset,
		RISE_FALL 		=> RISE_FALL,
		CONVERT 	 	=> CONVERT,
		OSC_CNTRL 		=> OSC_CNTRL,

		-- Miscellaneous Signals
		ADC_DATA		=> ADC_DATA,
		Reset_Button		=> Reset_Button,


		-- StateMachine Specific Signals
		Mux_Sel			=> Mux_Sel,
		statemachine_sram_enn	=> statemachine_sram_enn,
		statemachine_we		=> statemachine_we,
		statemachine_oe		=> statemachine_oe,
		SM_ADDRESS		=> SM_ADDRESS,
		SM_WE			=> SM_WE );

 
	dout <= '1';
 
	-- ******************** Process: GEN_CLOCK ********************
	-- Generate 2.5 MHz clock from ADC
	GEN_CLOCK: process
	begin

		Cclk <= '0';
		wait for 800 nS;

		loop
			Cclk <= not(Cclk) after CLOCKSKEW;
			wait for HALFCLOCKPERIOD;

		end loop;

	end process GEN_CLOCK;


	-- ******************** Process: GEN_RESET ********************
	-- Generate RESET_BUTTON
	GEN_RESET: process
	begin
		Reset_Button <= '1';
		wait for 200 nS;

		Reset_Button <= '0';
		wait for 400 nS;
		
		Reset_Button <= '1';
		wait;

	end process GEN_RESET;
	

end BEHAVIOR;