time_sim.vhd

Serial ADC Interface write in VHDL based on xilinx cpld

               and not dvm_main_curr_state_D2_Q_tF 
               and dvm_wr_reg_num_0_Q_tF and not dvm_wr_reg_num_2_Q_tF)
               or (dvm_main_curr_state_D3_Q_tF 
               and not dvm_wr_addr4_flag_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF 
               and dvm_main_curr_state_D1_Q_tF and N1636_COM_tF 
               and not dvm_main_curr_state_D2_Q_tF 
               and not dvm_wr_addr5_flag_Q_tF 
               and not dvm_wr_addr6_flag_Q_tF 
               and not dvm_wr_addr3_flag_Q_tF 
               and not dvm_wr_addr7_flag_Q_tF and dvm_wr_addr24_flag_Q_tF)
               or (not dvm_main_curr_state_D3_Q_tF 
               and dvm_wr_reg_num_1_Q_tF and not N_PZ_3811_COM_tF 
               and dvm_main_curr_state_D4_Q_tF and N1636_COM_tF 
               and not dvm_main_curr_state_D2_Q_tF 
               and dvm_wr_reg_num_0_Q_tF and dvm_wr_reg_num_2_Q_tF))
               after tLOGI2;
--------( a[0] )-----------------------------------------------------------
a_0_COM     <= not ((not sp_a_1_tIN and dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF)
               or (N_PZ_3771_COM_tF and not dvm_I_sm_address_0_Q_tF))
               after tLOGI2;
a_0_OE      <= (VCC) after tFIN;
a_0_buf: pxa_bufif2 port map (a(0), a_0_COM, a_0_OE, GND);
--------( a[10] )----------------------------------------------------------
a_10_COM    <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF and not sp_a_11_tIN 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF)
               or (N_PZ_3771_COM_tF and not dvm_I_sm_address_10_Q_tF))
               after tLOGI2;
a_10_OE     <= (VCC) after tFIN;
a_10_buf: pxa_bufif2 port map (a(10), a_10_COM, a_10_OE, GND);
--------( a[11] )----------------------------------------------------------
a_11_COM    <= not ((dvm_main_curr_state_D3_Q_tF and not sp_a_12_tIN 
               and not dvm_main_curr_state_D2_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF)
               or (N_PZ_3771_COM_tF and not dvm_I_sm_address_11_Q_tF))
               after tLOGI2;
a_11_OE     <= (VCC) after tFIN;
a_11_buf: pxa_bufif2 port map (a(11), a_11_COM, a_11_OE, GND);
--------( a[12] )----------------------------------------------------------
a_12_COM    <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF and not sp_a_13_tIN 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF)
               or (N_PZ_3771_COM_tF and not dvm_I_sm_address_12_Q_tF))
               after tLOGI2;
a_12_OE     <= (VCC) after tFIN;
a_12_buf: pxa_bufif2 port map (a(12), a_12_COM, a_12_OE, GND);
--------( a[13] )----------------------------------------------------------
a_13_COM    <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF and not sp_a_14_tIN)
               or (not dvm_I_sm_address_13_Q_tF and N_PZ_3771_COM_tF))
               after tLOGI2;
a_13_OE     <= (VCC) after tFIN;
a_13_buf: pxa_bufif2 port map (a(13), a_13_COM, a_13_OE, GND);
--------( a[14] )----------------------------------------------------------
a_14_COM    <= not ((dvm_main_curr_state_D3_Q_tF and not sp_a_15_tIN 
               and not dvm_main_curr_state_D2_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF)
               or (not dvm_I_sm_address_14_Q_tF and N_PZ_3771_COM_tF))
               after tLOGI2;
a_14_OE     <= (VCC) after tFIN;
a_14_buf: pxa_bufif2 port map (a(14), a_14_COM, a_14_OE, GND);
--------( a[15] )----------------------------------------------------------
a_15_COM    <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF and not sp_a_16_tIN)
               or (not dvm_I_sm_address_15_Q_tF and N_PZ_3771_COM_tF))
               after tLOGI2;
a_15_OE     <= (VCC) after tFIN;
a_15_buf: pxa_bufif2 port map (a(15), a_15_COM, a_15_OE, GND);
--------( a[16] )----------------------------------------------------------
a_16_COM    <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF and not sp_a_17_tIN 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF)
               or (not dvm_I_sm_address_16_Q_tF and N_PZ_3771_COM_tF))
               after tLOGI2;
a_16_OE     <= (VCC) after tFIN;
a_16_buf: pxa_bufif2 port map (a(16), a_16_COM, a_16_OE, GND);
--------( a[17] )----------------------------------------------------------
a_17_COM    <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF and not sp_a_18_tIN 
               and not dvm_main_curr_state_D2_Q_tF)
               or (not dvm_I_sm_address_17_Q_tF and N_PZ_3771_COM_tF))
               after tLOGI2;
a_17_OE     <= (VCC) after tFIN;
a_17_buf: pxa_bufif2 port map (a(17), a_17_COM, a_17_OE, GND);
--------( a[18] )----------------------------------------------------------
a_18_COM    <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF and not sp_a_19_tIN)
               or (N_PZ_3771_COM_tF and not dvm_I_sm_address_18_Q_tF))
               after tLOGI2;
a_18_OE     <= (VCC) after tFIN;
a_18_buf: pxa_bufif2 port map (a(18), a_18_COM, a_18_OE, GND);
--------( a[19] )----------------------------------------------------------
a_19_COM    <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF and not sp_a_20_tIN)
               or (N_PZ_3771_COM_tF and not dvm_I_sm_address_19_Q_tF))
               after tLOGI2;
a_19_OE     <= (VCC) after tFIN;
a_19_buf: pxa_bufif2 port map (a(19), a_19_COM, a_19_OE, GND);
--------( a[1] )-----------------------------------------------------------
a_1_COM     <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF and not sp_a_2_tIN 
               and not dvm_main_curr_state_D2_Q_tF)
               or (not dvm_I_sm_address_1_Q_tF and N_PZ_3771_COM_tF))
               after tLOGI2;
a_1_OE      <= (VCC) after tFIN;
a_1_buf: pxa_bufif2 port map (a(1), a_1_COM, a_1_OE, GND);
--------( a[20] )----------------------------------------------------------
a_20_COM    <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF and not sp_a_21_tIN 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF)
               or (not dvm_I_sm_address_20_Q_tF and N_PZ_3771_COM_tF))
               after tLOGI2;
a_20_OE     <= (VCC) after tFIN;
a_20_buf: pxa_bufif2 port map (a(20), a_20_COM, a_20_OE, GND);
--------( a[21] )----------------------------------------------------------
a_21_COM    <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF and not sp_a_22_tIN)
               or (not dvm_I_sm_address_21_Q_tF and N_PZ_3771_COM_tF))
               after tLOGI2;
a_21_OE     <= (VCC) after tFIN;
a_21_buf: pxa_bufif2 port map (a(21), a_21_COM, a_21_OE, GND);
--------( a[22] )----------------------------------------------------------
a_22_COM    <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF and not sp_a_23_tIN)
               or (N_PZ_3771_COM_tF and not dvm_I_sm_address_22_Q_tF))
               after tLOGI2;
a_22_OE     <= (VCC) after tFIN;
a_22_buf: pxa_bufif2 port map (a(22), a_22_COM, a_22_OE, GND);
--------( a[2] )-----------------------------------------------------------
a_2_COM     <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF and not sp_a_3_tIN 
               and not dvm_main_curr_state_D2_Q_tF)
               or (not dvm_I_sm_address_2_Q_tF and N_PZ_3771_COM_tF))
               after tLOGI2;
a_2_OE      <= (VCC) after tFIN;
a_2_buf: pxa_bufif2 port map (a(2), a_2_COM, a_2_OE, GND);
--------( a[3] )-----------------------------------------------------------
a_3_COM     <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF and not sp_a_4_tIN)
               or (not dvm_I_sm_address_3_Q_tF and N_PZ_3771_COM_tF))
               after tLOGI2;
a_3_OE      <= (VCC) after tFIN;
a_3_buf: pxa_bufif2 port map (a(3), a_3_COM, a_3_OE, GND);
--------( a[4] )-----------------------------------------------------------
a_4_COM     <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF and not sp_a_5_tIN)
               or (N_PZ_3771_COM_tF and not dvm_I_sm_address_4_Q_tF))
               after tLOGI2;
a_4_OE      <= (VCC) after tFIN;
a_4_buf: pxa_bufif2 port map (a(4), a_4_COM, a_4_OE, GND);
--------( a[5] )-----------------------------------------------------------
a_5_COM     <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF and not sp_a_6_tIN 
               and not dvm_main_curr_state_D4_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF)
               or (N_PZ_3771_COM_tF and not dvm_I_sm_address_5_Q_tF))
               after tLOGI2;
a_5_OE      <= (VCC) after tFIN;
a_5_buf: pxa_bufif2 port map (a(5), a_5_COM, a_5_OE, GND);
--------( a[6] )-----------------------------------------------------------
a_6_COM     <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF and not sp_a_7_tIN 
               and not dvm_main_curr_state_D4_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF)
               or (N_PZ_3771_COM_tF and not dvm_I_sm_address_6_Q_tF))
               after tLOGI2;
a_6_OE      <= (VCC) after tFIN;
a_6_buf: pxa_bufif2 port map (a(6), a_6_COM, a_6_OE, GND);
--------( a[7] )-----------------------------------------------------------
a_7_COM     <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF and not sp_a_8_tIN)
               or (N_PZ_3771_COM_tF and not dvm_I_sm_address_7_Q_tF))
               after tLOGI2;
a_7_OE      <= (VCC) after tFIN;
a_7_buf: pxa_bufif2 port map (a(7), a_7_COM, a_7_OE, GND);
--------( a[8] )-----------------------------------------------------------
a_8_COM     <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF and not sp_a_9_tIN 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF)
               or (N_PZ_3771_COM_tF and not dvm_I_sm_address_8_Q_tF))
               after tLOGI2;
a_8_OE      <= (VCC) after tFIN;
a_8_buf: pxa_bufif2 port map (a(8), a_8_COM, a_8_OE, GND);
--------( a[9] )-----------------------------------------------------------
a_9_COM     <= not ((dvm_main_curr_state_D3_Q_tF 
               and not dvm_main_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D4_Q_tF and not sp_a_10_tIN 
               and not dvm_main_curr_state_D2_Q_tF)
               or (not dvm_I_sm_address_9_Q_tF and N_PZ_3771_COM_tF))
               after tLOGI2;
a_9_OE      <= (VCC) after tFIN;
a_9_buf: pxa_bufif2 port map (a(9), a_9_COM, a_9_OE, GND);
--------( ad_chip2_enn )---------------------------------------------------
ad_chip2_enn_COM<= ((not dvm_shift_curr_state_D2_Q_tF 
               and dvm_main_curr_state_D1_Q_tF 
               and not dvm_shift_curr_state_D1_Q_tF 
               and not dvm_main_curr_state_D2_Q_tF 
               and not dvm_main_curr_state_D