📄 time_sim.vhd
字号:
dvm_I_sm_address_1_C, dvm_I_sm_address_1_DIN,
dvm_I_sm_address_1_Q, dvm_I_sm_address_1_Q_tF,
dvm_I_sm_address_1_T, dvm_I_sm_address_20_AP,
dvm_I_sm_address_20_AR, dvm_I_sm_address_20_C,
dvm_I_sm_address_20_DIN, dvm_I_sm_address_20_Q,
dvm_I_sm_address_20_Q_tF, dvm_I_sm_address_20_T,
dvm_I_sm_address_21_AP, dvm_I_sm_address_21_AR,
dvm_I_sm_address_21_C, dvm_I_sm_address_21_DIN,
dvm_I_sm_address_21_Q, dvm_I_sm_address_21_Q_tF,
dvm_I_sm_address_21_T, dvm_I_sm_address_22_AP,
dvm_I_sm_address_22_AR, dvm_I_sm_address_22_C,
dvm_I_sm_address_22_DIN, dvm_I_sm_address_22_Q,
dvm_I_sm_address_22_Q_tF, dvm_I_sm_address_22_T,
dvm_I_sm_address_2_AP, dvm_I_sm_address_2_AR,
dvm_I_sm_address_2_C, dvm_I_sm_address_2_DIN,
dvm_I_sm_address_2_Q, dvm_I_sm_address_2_Q_tF,
dvm_I_sm_address_2_T, dvm_I_sm_address_3_AP,
dvm_I_sm_address_3_AR, dvm_I_sm_address_3_C, dvm_I_sm_address_3_D,
dvm_I_sm_address_3_DIN, dvm_I_sm_address_3_Q,
dvm_I_sm_address_3_Q_tF, dvm_I_sm_address_4_AP,
dvm_I_sm_address_4_AR, dvm_I_sm_address_4_C, dvm_I_sm_address_4_D,
dvm_I_sm_address_4_DIN, dvm_I_sm_address_4_Q,
dvm_I_sm_address_4_Q_tF, dvm_I_sm_address_5_AP,
dvm_I_sm_address_5_AR, dvm_I_sm_address_5_C,
dvm_I_sm_address_5_DIN, dvm_I_sm_address_5_Q,
dvm_I_sm_address_5_Q_tF, dvm_I_sm_address_5_T,
dvm_I_sm_address_6_AP, dvm_I_sm_address_6_AR,
dvm_I_sm_address_6_C, dvm_I_sm_address_6_D,
dvm_I_sm_address_6_DIN, dvm_I_sm_address_6_Q,
dvm_I_sm_address_6_Q_tF, dvm_I_sm_address_7_AP,
dvm_I_sm_address_7_AR, dvm_I_sm_address_7_C, dvm_I_sm_address_7_D,
dvm_I_sm_address_7_DIN, dvm_I_sm_address_7_Q,
dvm_I_sm_address_7_Q_tF, dvm_I_sm_address_8_AP,
dvm_I_sm_address_8_AR, dvm_I_sm_address_8_C,
dvm_I_sm_address_8_DIN, dvm_I_sm_address_8_Q,
dvm_I_sm_address_8_Q_tF, dvm_I_sm_address_8_T,
dvm_I_sm_address_9_AP, dvm_I_sm_address_9_AR,
dvm_I_sm_address_9_C, dvm_I_sm_address_9_DIN,
dvm_I_sm_address_9_Q, dvm_I_sm_address_9_Q_tF,
dvm_I_sm_address_9_T, dvm_addr_set_AP, dvm_addr_set_AR,
dvm_addr_set_C, dvm_addr_set_D, dvm_addr_set_DIN, dvm_addr_set_Q,
dvm_addr_set_Q_tF, dvm_cnt5_q_int_0_AP, dvm_cnt5_q_int_0_AR,
dvm_cnt5_q_int_0_C, dvm_cnt5_q_int_0_CE, dvm_cnt5_q_int_0_D,
dvm_cnt5_q_int_0_DIN, dvm_cnt5_q_int_0_Q, dvm_cnt5_q_int_0_Q_tF,
dvm_cnt5_q_int_1_AP, dvm_cnt5_q_int_1_AR, dvm_cnt5_q_int_1_C,
dvm_cnt5_q_int_1_DIN, dvm_cnt5_q_int_1_Q, dvm_cnt5_q_int_1_Q_tF,
dvm_cnt5_q_int_1_T, dvm_cnt5_q_int_2_AP, dvm_cnt5_q_int_2_AR,
dvm_cnt5_q_int_2_C, dvm_cnt5_q_int_2_DIN, dvm_cnt5_q_int_2_Q,
dvm_cnt5_q_int_2_Q_tF, dvm_cnt5_q_int_2_T, dvm_cnt5_q_int_3_AP,
dvm_cnt5_q_int_3_AR, dvm_cnt5_q_int_3_C, dvm_cnt5_q_int_3_DIN,
dvm_cnt5_q_int_3_Q, dvm_cnt5_q_int_3_Q_tF, dvm_cnt5_q_int_3_T,
dvm_cnt5_q_int_4_AP, dvm_cnt5_q_int_4_AR, dvm_cnt5_q_int_4_C,
dvm_cnt5_q_int_4_DIN, dvm_cnt5_q_int_4_Q, dvm_cnt5_q_int_4_Q_tF,
dvm_cnt5_q_int_4_T, dvm_dm_num_0_AP, dvm_dm_num_0_AR,
dvm_dm_num_0_C, dvm_dm_num_0_D, dvm_dm_num_0_DIN, dvm_dm_num_0_Q,
dvm_dm_num_0_Q_tF, dvm_dm_num_1_AP, dvm_dm_num_1_AR,
dvm_dm_num_1_C, dvm_dm_num_1_D, dvm_dm_num_1_DIN, dvm_dm_num_1_Q,
dvm_dm_num_1_Q_tF, dvm_dm_num_2_AP, dvm_dm_num_2_AR,
dvm_dm_num_2_C, dvm_dm_num_2_DIN, dvm_dm_num_2_Q,
dvm_dm_num_2_Q_tF, dvm_dm_num_2_T, dvm_dm_sng_ln0_flag_AP,
dvm_dm_sng_ln0_flag_AR, dvm_dm_sng_ln0_flag_C,
dvm_dm_sng_ln0_flag_D, dvm_dm_sng_ln0_flag_DIN,
dvm_dm_sng_ln0_flag_Q, dvm_dm_sng_ln0_flag_Q_tF,
dvm_dm_sng_ln1_flag_AP, dvm_dm_sng_ln1_flag_AR,
dvm_dm_sng_ln1_flag_C, dvm_dm_sng_ln1_flag_D,
dvm_dm_sng_ln1_flag_DIN, dvm_dm_sng_ln1_flag_Q,
dvm_dm_sng_ln1_flag_Q_tF, dvm_dm_sng_ln2_flag_AP,
dvm_dm_sng_ln2_flag_AR, dvm_dm_sng_ln2_flag_C,
dvm_dm_sng_ln2_flag_D, dvm_dm_sng_ln2_flag_DIN,
dvm_dm_sng_ln2_flag_Q, dvm_dm_sng_ln2_flag_Q_tF,
dvm_dm_sng_ln3_flag_AP, dvm_dm_sng_ln3_flag_AR,
dvm_dm_sng_ln3_flag_C, dvm_dm_sng_ln3_flag_D,
dvm_dm_sng_ln3_flag_DIN, dvm_dm_sng_ln3_flag_Q,
dvm_dm_sng_ln3_flag_Q_tF, dvm_dm_sng_ln4_flag_AP,
dvm_dm_sng_ln4_flag_AR, dvm_dm_sng_ln4_flag_C,
dvm_dm_sng_ln4_flag_D, dvm_dm_sng_ln4_flag_DIN,
dvm_dm_sng_ln4_flag_Q, dvm_dm_sng_ln4_flag_Q_tF,
dvm_dm_sng_ln5_flag_AP, dvm_dm_sng_ln5_flag_AR,
dvm_dm_sng_ln5_flag_C, dvm_dm_sng_ln5_flag_D,
dvm_dm_sng_ln5_flag_DIN, dvm_dm_sng_ln5_flag_Q,
dvm_dm_sng_ln5_flag_Q_tF, dvm_dm_sng_ln6_flag_AP,
dvm_dm_sng_ln6_flag_AR, dvm_dm_sng_ln6_flag_C,
dvm_dm_sng_ln6_flag_DIN, dvm_dm_sng_ln6_flag_Q,
dvm_dm_sng_ln6_flag_Q_tF, dvm_dm_sng_ln6_flag_T,
dvm_dm_sng_ln7_flag_AP, dvm_dm_sng_ln7_flag_AR,
dvm_dm_sng_ln7_flag_C, dvm_dm_sng_ln7_flag_D,
dvm_dm_sng_ln7_flag_DIN, dvm_dm_sng_ln7_flag_Q,
dvm_dm_sng_ln7_flag_Q_tF, dvm_main_curr_state_D1_AP,
dvm_main_curr_state_D1_AR, dvm_main_curr_state_D1_C,
dvm_main_curr_state_D1_DIN, dvm_main_curr_state_D1_Q,
dvm_main_curr_state_D1_Q_tF, dvm_main_curr_state_D1_T,
dvm_main_curr_state_D2_AP, dvm_main_curr_state_D2_AR,
dvm_main_curr_state_D2_C, dvm_main_curr_state_D2_DIN,
dvm_main_curr_state_D2_Q, dvm_main_curr_state_D2_Q_tF,
dvm_main_curr_state_D2_T, dvm_main_curr_state_D3_AP,
dvm_main_curr_state_D3_AR, dvm_main_curr_state_D3_C,
dvm_main_curr_state_D3_D, dvm_main_curr_state_D3_DIN,
dvm_main_curr_state_D3_Q, dvm_main_curr_state_D3_Q_tF,
dvm_main_curr_state_D4_AP, dvm_main_curr_state_D4_AR,
dvm_main_curr_state_D4_C, dvm_main_curr_state_D4_DIN,
dvm_main_curr_state_D4_Q, dvm_main_curr_state_D4_Q_tF,
dvm_main_curr_state_D4_T, dvm_shift_adc_data_int_0_AP,
dvm_shift_adc_data_int_0_AR, dvm_shift_adc_data_int_0_C,
dvm_shift_adc_data_int_0_CE, dvm_shift_adc_data_int_0_D,
dvm_shift_adc_data_int_0_DIN, dvm_shift_adc_data_int_0_Q,
dvm_shift_adc_data_int_0_Q_tF, dvm_shift_adc_data_int_10_AP,
dvm_shift_adc_data_int_10_AR, dvm_shift_adc_data_int_10_C,
dvm_shift_adc_data_int_10_CE, dvm_shift_adc_data_int_10_D,
dvm_shift_adc_data_int_10_DIN, dvm_shift_adc_data_int_10_Q,
dvm_shift_adc_data_int_10_Q_tF, dvm_shift_adc_data_int_11_AP,
dvm_shift_adc_data_int_11_AR, dvm_shift_adc_data_int_11_C,
dvm_shift_adc_data_int_11_CE, dvm_shift_adc_data_int_11_D,
dvm_shift_adc_data_int_11_DIN, dvm_shift_adc_data_int_11_Q,
dvm_shift_adc_data_int_11_Q_tF, dvm_shift_adc_data_int_12_AP,
dvm_shift_adc_data_int_12_AR, dvm_shift_adc_data_int_12_C,
dvm_shift_adc_data_int_12_CE, dvm_shift_adc_data_int_12_D,
dvm_shift_adc_data_int_12_DIN, dvm_shift_adc_data_int_12_Q,
dvm_shift_adc_data_int_12_Q_tF, dvm_shift_adc_data_int_13_AP,
dvm_shift_adc_data_int_13_AR, dvm_shift_adc_data_int_13_C,
dvm_shift_adc_data_int_13_CE, dvm_shift_adc_data_int_13_D,
dvm_shift_adc_data_int_13_DIN, dvm_shift_adc_data_int_13_Q,
dvm_shift_adc_data_int_13_Q_tF, dvm_shift_adc_data_int_14_AP,
dvm_shift_adc_data_int_14_AR, dvm_shift_adc_data_int_14_C,
dvm_shift_adc_data_int_14_CE, dvm_shift_adc_data_int_14_D,
dvm_shift_adc_data_int_14_DIN, dvm_shift_adc_data_int_14_Q,
dvm_shift_adc_data_int_14_Q_tF, dvm_shift_adc_data_int_15_AP,
dvm_shift_adc_data_int_15_AR, dvm_shift_adc_data_int_15_C,
dvm_shift_adc_data_int_15_CE, dvm_shift_adc_data_int_15_D,
dvm_shift_adc_data_int_15_DIN, dvm_shift_adc_data_int_15_Q,
dvm_shift_adc_data_int_15_Q_tF, dvm_shift_adc_data_int_1_AP,
dvm_shift_adc_data_int_1_AR, dvm_shift_adc_data_int_1_C,
dvm_shift_adc_data_int_1_CE, dvm_shift_adc_data_int_1_D,
dvm_shift_adc_data_int_1_DIN, dvm_shift_adc_data_int_1_Q,
dvm_shift_adc_data_int_1_Q_tF, dvm_shift_adc_data_int_2_AP,
dvm_shift_adc_data_int_2_AR, dvm_shift_adc_data_int_2_C,
dvm_shift_adc_data_int_2_CE, dvm_shift_adc_data_int_2_D,
dvm_shift_adc_data_int_2_DIN, dvm_shift_adc_data_int_2_Q,
dvm_shift_adc_data_int_2_Q_tF, dvm_shift_adc_data_int_3_AP,
dvm_shift_adc_data_int_3_AR, dvm_shift_adc_data_int_3_C,
dvm_shift_adc_data_int_3_CE, dvm_shift_adc_data_int_3_D,
dvm_shift_adc_data_int_3_DIN, dvm_shift_adc_data_int_3_Q,
dvm_shift_adc_data_int_3_Q_tF, dvm_shift_adc_data_int_4_AP,
dvm_shift_adc_data_int_4_AR, dvm_shift_adc_data_int_4_C,
dvm_shift_adc_data_int_4_CE, dvm_shift_adc_data_int_4_D,
dvm_shift_adc_data_int_4_DIN, dvm_shift_adc_data_int_4_Q,
dvm_shift_adc_data_int_4_Q_tF, dvm_shift_adc_data_int_5_AP,
dvm_shift_adc_data_int_5_AR, dvm_shift_adc_data_int_5_C,
dvm_shift_adc_data_int_5_CE, dvm_shift_adc_data_int_5_D,
dvm_shift_adc_data_int_5_DIN, dvm_shift_adc_data_int_5_Q,
dvm_shift_adc_data_int_5_Q_tF, dvm_shift_adc_data_int_6_AP,
dvm_shift_adc_data_int_6_AR, dvm_shift_adc_data_int_6_C,
dvm_shift_adc_data_int_6_CE, dvm_shift_adc_data_int_6_D,
dvm_shift_adc_data_int_6_DIN, dvm_shift_adc_data_int_6_Q,
dvm_shift_adc_data_int_6_Q_tF, dvm_shift_adc_data_int_7_AP,
dvm_shift_adc_data_int_7_AR, dvm_shift_adc_data_int_7_C,
dvm_shift_adc_data_int_7_CE, dvm_shift_adc_data_int_7_D,
dvm_shift_adc_data_int_7_DIN, dvm_shift_adc_data_int_7_Q,
dvm_shift_adc_data_int_7_Q_tF, dvm_shift_adc_data_int_8_AP,
dvm_shift_adc_data_int_8_AR, dvm_shift_adc_data_int_8_C,
dvm_shift_adc_data_int_8_CE, dvm_shift_adc_data_int_8_D,
dvm_shift_adc_data_int_8_DIN, dvm_shift_adc_data_int_8_Q,
dvm_shift_adc_data_int_8_Q_tF, dvm_shift_adc_data_int_9_AP,
dvm_shift_adc_data_int_9_AR, dvm_shift_adc_data_int_9_C,
dvm_shift_adc_data_int_9_CE, dvm_shift_adc_data_int_9_D,
dvm_shift_adc_data_int_9_DIN, dvm_shift_adc_data_int_9_Q,
dvm_shift_adc_data_int_9_Q_tF, dvm_shift_curr_state_D1_AP,
dvm_shift_curr_state_D1_AR, dvm_shift_curr_state_D1_C,
dvm_shift_curr_state_D1_D, dvm_shift_curr_state_D1_DIN,
dvm_shift_curr_state_D1_Q, dvm_shift_curr_state_D1_Q_tF,
dvm_shift_curr_state_D2_AP, dvm_shift_curr_state_D2_AR,
dvm_shift_curr_state_D2_C, dvm_shift_curr_state_D2_D,
dvm_shift_curr_state_D2_DIN, dvm_shift_curr_state_D2_Q,
dvm_shift_curr_state_D2_Q_tF, dvm_shift_data_data_int_0_AP,
dvm_shift_data_data_int_0_AR, dvm_shift_data_data_int_0_C,
dvm_shift_data_data_int_0_CE, dvm_shift_data_data_int_0_D,
dvm_shift_data_data_int_0_DIN, dvm_shift_data_data_int_0_Q,
dvm_shift_data_data_int_0_Q_tF, dvm_shift_data_data_int_1_AP,
dvm_shift_data_data_int_1_AR, dvm_shift_data_data_int_1_C,
dvm_shift_data_data_int_1_CE, dvm_shift_data_data_int_1_D,
dvm_shift_data_data_int_1_DIN, dvm_shift_data_data_int_1_Q,
dvm_shift_data_data_int_1_Q_tF, dvm_shift_data_data_int_2_AP,
dvm_shift_data_data_int_2_AR, dvm_shift_data_data_int_2_C,
dvm_shift_data_data_int_2_CE, dvm_shift_data_data_int_2_D,
dvm_shift_data_data_int_2_DIN, dvm_shift_data_data_int_2_Q,
dvm_shift_data_data_int_2_Q_tF, dvm_shift_data_data_int_3_AP,
dvm_shift_data_data_int_3_AR, dvm_shift_data_data_int_3_C,
dvm_shift_data_data_int_3_CE, dvm_shift_data_data_int_3_D,
dvm_shift_data_data_int_3_DIN, dvm_shift_data_data_int_3_Q,
dvm_shift_data_data_int_3_Q_tF, dvm_shift_data_data_int_4_AP,
dvm_shift_data_data_int_4_AR, dvm_shift_data_data_int_4_C,
dvm_shift_data_data_int_4_CE, dvm_shift_data_data_int_4_D,
dvm_shift_data_data_int_4_DIN, dvm_shift_data_data_int_4_Q,
dvm_shift_data_data_int_4_Q_tF, dvm_shift_data_data_int_5_AP,
dvm_shift_data_data_int_5_AR, dvm_shift_data_data_int_5_C,
dvm_shift_data_data_int_5_CE, dvm_shift_data_data_int_5_D,
dvm_shift_data_data_int_5_DIN, dvm_shift_data_data_int_5_Q,
dvm_shift_data_data_int_5_Q_tF, dvm_shift_data_data_int_6_AP,
dvm_shift_data_data_int_6_AR, dvm_shift_data_data_int_6_C,
dvm_shift_data_data_int_6_CE, dvm_shift_data_data_int_6_D,
dvm_shift_data_data_int_6_DIN, dvm_shift_data_data_int_6_Q,
dvm_shift_data_data_int_6_Q_tF, dvm_shift_data_data_int_7_AP,
dvm_shift_data_data_int_7_AR, dvm_shift_data_data_int_7_C,
dvm_shift_data_data_int_7_CE, dvm_shift_data_data_int_7_D,
dvm_shift_data_data_int_7_DIN, dvm_shift_data_data_int_7_Q,
dvm_shift_data_data_int_7_Q_tF, dvm_wr_addr24_flag_AP,
dvm_wr_addr24_flag_AR, dvm_wr_addr24_flag_C, dvm_wr_addr24_flag_D,
dvm_wr_addr24_flag_DIN, dvm_wr_addr24_flag_Q,
dvm_wr_addr24_flag_Q_tF, dvm_wr_addr3_flag_AP,
dvm_wr_addr3_flag_AR, dvm_wr_addr3_flag_C, dvm_wr_addr3_flag_DIN,
dvm_wr_addr3_flag_Q, dvm_wr_addr3_flag_Q_tF, dvm_wr_addr3_flag_T,
dvm_wr_addr4_flag_AP, dvm_wr_addr4_flag_AR, dvm_wr_addr4_flag_C,
dvm_wr_addr4_flag_D, dvm_wr_addr4_flag_DIN, dvm_wr_addr4_flag_Q,
dvm_wr_addr4_flag_Q_tF, dvm_wr_addr5_flag_AP,
dvm_wr_addr5_flag_AR, dvm_wr_addr5_flag_C, dvm_wr_addr5_flag_DIN,
dvm_wr_addr5_flag_Q, dvm_wr_addr5_flag_Q_tF, dvm_wr_addr5_flag_T,
dvm_wr_addr6_flag_AP, dvm_wr_addr6_flag_AR, dvm_wr_addr6_flag_C,
dvm_wr_addr6_flag_D, dvm_wr_addr6_flag_DIN, dvm_wr_addr6_flag_Q,
dvm_wr_addr6_flag_Q_tF, dvm_wr_addr7_flag_AP,
dvm_wr_addr7_flag_AR, dvm_wr_addr7_flag_C, dvm_wr_addr7_flag_D,
dvm_wr_addr7_flag_DIN, dvm_wr_addr7_flag_Q,
dvm_wr_addr7_flag_Q_tF, dvm_wr_reg_num_0_AP, dvm_wr_reg_num_0_AR,
dvm_wr_reg_num_0_C, dvm_wr_reg_num_0_DIN, dvm_wr_reg_num_0_Q,
dvm_wr_reg_num_0_Q_tF, dvm_wr_reg_num_0_T, dvm_wr_reg_num_1_AP,
dvm_wr_reg_num_1_AR, dvm_wr_reg_num_1_C, dvm_wr_reg_num_1_DIN,
dvm_wr_reg_num_1_Q, dvm_wr_reg_num_1_Q_tF, dvm_wr_reg_num_1_T,
dvm_wr_reg_num_2_AP, dvm_wr_reg_num_2_AR, dvm_wr_reg_num_2_C,
dvm_wr_reg_num_2_DIN, dvm_wr_reg_num_2_Q, dvm_wr_reg_num_2_Q_tF,
dvm_wr_reg_num_2_T, flash_cs0n_COM, flash_cs0n_OE,
flash_wr_protect_COM, flash_wr_protect_OE, io13_COM, io13_OE,
led1_sel_COM, led1_sel_OE, led2_sel_COM, led2_sel_OE,
led3_sel_COM, led3_sel_OE, led4_sel_COM, led4_sel_OE, oen_COM,
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -