time_sim.vhd

Serial ADC Interface write in VHDL based on xilinx cpld

---------------------------------------------------------------------------
-- XPLAOPT Version 3.42
-- VHDL Timing Model
-- Converted from JEDEC file
-- Created by Xilinx, Inc.
-- Design Name = top_level.blx
-- Device Name = XCR3256XL-7CS280
-- Apr 19 14:07:30 2001
---------------------------------------------------------------------------
package pxa_pkg is
    constant tLOGI1 : time := 2000 ps;
    constant tLOGI2 : time := 2500 ps;
    constant tLOGI3 : time := 6000 ps;
    constant tFIN  : time := 2200 ps;
    constant tIN   : time := 2500 ps;
    constant tF    : time := 2800 ps;
    constant tUDA  : time := 4000 ps;
    constant tGCK  : time := 1000 ps;
    constant tLDI  : time := 1300 ps;
    constant toe_slew : time := 8500 ps;
    constant tbuf_slew : time := 6500 ps;
    constant tap2q : time := 2000 ps;
    constant tar2q : time := 2000 ps;
    constant trd   : time := 1000 ps;
    constant tbuf  : time := 2500 ps;
    constant toe   : time := 4500 ps;
end pxa_pkg;
---------------------------------------------------------------------------
-- Components Defined Here
---------------------------------------------------------------------------
-- Output Buffer
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_bufif2 is
	port (O: out std_logic; I, OE, SLEW : in std_logic);
end pxa_bufif2;
architecture behavioral of pxa_bufif2 is
signal OE_local, I_local : std_logic := '0';
begin
  OE_local <= OE after toe_slew when SLEW = '1' else OE after toe;
  I_local <= I after tbuf_slew when SLEW = '1' else I after tbuf;
  O <= I_local when OE_local = '1' else 'Z';
end behavioral;

-- Multiplexer
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_mux is
	port (O: out std_logic; S, A, B : in std_logic);
end pxa_mux;
architecture behavioral of pxa_mux is
begin
	O <= A when S = '1' else B;
end behavioral;

-- D Flip Flop with Asynchronous Preset/Reset; Power up to 0.
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_dff_apar_p0 is
	port (Q : out std_logic; D, CLK, AP, AR : in std_logic);
end pxa_dff_apar_p0;
architecture behavioral of pxa_dff_apar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AP, AR)
  begin
    if AR = '1' then
	   Q_local <= '0' after tar2q;
    elsif AP = '1' then
	   Q_local <= '1' after tap2q;
    elsif rising_edge(CLK) then
	   Q_local <= D after trd;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

-- T Flip Flop with Asynchronous Preset/Reset; Power up to 0.
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_tff_apar_p0 is
	port (Q : out std_logic; T, CLK, AP, AR : in std_logic);
end pxa_tff_apar_p0;
architecture behavioral of pxa_tff_apar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AP, AR)
  begin
    if AR = '1' then
      Q_local <= '0' after tar2q;
    elsif AP = '1' then
      Q_local <= '1' after tap2q;
    elsif rising_edge(CLK) then
      if T = '1' then
        Q_local <= not Q_local after trd ;
      end if;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

-- D Flip Flop with Clock Enable and Asyn Preset/Reset; Power up to 0.
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_dff_ce_apar_p0 is
	port (Q : out std_logic; D, CLK, CE, AP, AR : in std_logic);
end pxa_dff_ce_apar_p0;
architecture behavioral of pxa_dff_ce_apar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, CE, AP, AR)
  begin
    if AR = '1' then
	   Q_local <= '0' after tar2q;
    elsif AP = '1' then
	   Q_local <= '1' after tap2q;
    elsif rising_edge(CLK) then
      if CE = '1' then
        Q_local <= D after trd;
      end if;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

---------------------------------------------------------------------------
-- Main VHDL Model 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity top_level is
    port(busy, cclk, dout, sp_cs0n, sp_cs1n, sp_oen, sp_wen: in std_logic;
         sp_a: in std_logic_vector(23 downto 1);
         ad_chip2_enn, ads_reset, busy_test, chip3_en, convert, din,
         flash_cs0n, flash_wr_protect, io13, led1_sel, led2_sel, led3_sel,
         led4_sel, oen, osc_cntrl, rise_fall, rwn, sclk, sp_a_0, sram_cs1n,
         sram_low_byten, sram_upper_byten: out std_logic;
         a: out std_logic_vector(22 downto 0);
         d: inout std_logic_vector(15 downto 0);
         sp_d: inout std_logic_vector(15 downto 0)
         );
end top_level;

architecture structure of top_level is

-------- Signal Declaration -----------------------------------------------
signal   A_0_N117_COM, A_0_N117_COM_tF, A_0_N143_COM, A_0_N143_COM_tF,
         A_0_N259_COM, A_0_N259_COM_tF, N1002_COM, N1002_COM_tF, N1010_COM,
         N1010_COM_tF, N1181_COM, N1181_COM_tF, N1370_COM, N1370_COM_tF,
         N1636_COM, N1636_COM_tF, N1683_COM, N1683_COM_tF, N1835_COM,
         N1835_COM_tF, N1860_COM, N1860_COM_tF, N1868_COM, N1868_COM_tF,
         N2044_COM, N2044_COM_tF, N2058_COM, N2058_COM_tF, N2066_COM,
         N2066_COM_tF, N2083_COM, N2083_COM_tF, N2125_COM, N2125_COM_tF,
         N2141_COM, N2141_COM_tF, N2157_COM, N2157_COM_tF, N2190_COM,
         N2190_COM_tF, N2209_COM, N2209_COM_tF, N2403_COM, N2403_COM_tF,
         N2609_COM, N2609_COM_tF, N2634_COM, N2634_COM_tF, N2642_COM,
         N2642_COM_tF, N2671_COM, N2671_COM_tF, N872_COM, N872_COM_tF,
         N888_COM, N888_COM_tF, N904_COM, N904_COM_tF, N914_COM,
         N914_COM_tF, N916_COM, N916_COM_tF, N970_COM, N970_COM_tF,
         N977_COM, N977_COM_tF, N982_COM, N982_COM_tF, N_PZ_3685_COM,
         N_PZ_3685_COM_tF, N_PZ_3686_COM, N_PZ_3686_COM_tF, N_PZ_3771_COM,
         N_PZ_3771_COM_tF, N_PZ_3775_COM, N_PZ_3775_COM_tF, N_PZ_3780_COM,
         N_PZ_3780_COM_tF, N_PZ_3787_COM, N_PZ_3787_COM_tF, N_PZ_3799_COM,
         N_PZ_3799_COM_tF, N_PZ_3803_COM, N_PZ_3803_COM_tF, N_PZ_3811_COM,
         N_PZ_3811_COM_tF, N_PZ_3826_COM, N_PZ_3826_COM_tF, N_PZ_3833_COM,
         N_PZ_3833_COM_tF, N_PZ_3872_COM, N_PZ_3872_COM_tF, N_PZ_3893_COM,
         N_PZ_3893_COM_tF, N_PZ_3900_COM, N_PZ_3900_COM_tF, N_PZ_3917_COM,
         N_PZ_3917_COM_tF, N_PZ_3918_COM, N_PZ_3918_COM_tF, N_PZ_3924_COM,
         N_PZ_3924_COM_tF, a_0_COM, a_0_OE, a_10_COM, a_10_OE, a_11_COM,
         a_11_OE, a_12_COM, a_12_OE, a_13_COM, a_13_OE, a_14_COM, a_14_OE,
         a_15_COM, a_15_OE, a_16_COM, a_16_OE, a_17_COM, a_17_OE, a_18_COM,
         a_18_OE, a_19_COM, a_19_OE, a_1_COM, a_1_OE, a_20_COM, a_20_OE,
         a_21_COM, a_21_OE, a_22_COM, a_22_OE, a_2_COM, a_2_OE, a_3_COM,
         a_3_OE, a_4_COM, a_4_OE, a_5_COM, a_5_OE, a_6_COM, a_6_OE,
         a_7_COM, a_7_OE, a_8_COM, a_8_OE, a_9_COM, a_9_OE,
         ad_chip2_enn_COM, ad_chip2_enn_OE, ads_reset_COM, ads_reset_OE,
         busy_tIN, busy_test_COM, busy_test_OE, chip3_en_COM, chip3_en_OE,
         convert_COM, convert_OE, d_0_COM, d_0_OE, d_0_tIN, d_10_COM,
         d_10_OE, d_10_tIN, d_11_COM, d_11_OE, d_11_tIN, d_12_COM, d_12_OE,
         d_12_tIN, d_13_COM, d_13_OE, d_13_tIN, d_14_COM, d_14_OE,
         d_14_tIN, d_15_COM, d_15_OE, d_15_tIN, d_1_COM, d_1_OE, d_1_tIN,
         d_2_COM, d_2_OE, d_2_tIN, d_3_COM, d_3_OE, d_3_tIN, d_4_COM,
         d_4_OE, d_4_tIN, d_5_COM, d_5_OE, d_5_tIN, d_6_COM, d_6_OE,
         d_6_tIN, d_7_COM, d_7_OE, d_7_tIN, d_8_COM, d_8_OE, d_8_tIN,
         d_9_COM, d_9_OE, d_9_tIN, din_AP, din_AR, din_C, din_CE, din_D,
         din_DIN, din_OE, din_Q, dvm_I_sm_address_0_AP,
         dvm_I_sm_address_0_AR, dvm_I_sm_address_0_C,
         dvm_I_sm_address_0_DIN, dvm_I_sm_address_0_Q,
         dvm_I_sm_address_0_Q_tF, dvm_I_sm_address_0_T,
         dvm_I_sm_address_10_AP, dvm_I_sm_address_10_AR,
         dvm_I_sm_address_10_C, dvm_I_sm_address_10_D,
         dvm_I_sm_address_10_DIN, dvm_I_sm_address_10_Q,
         dvm_I_sm_address_10_Q_tF, dvm_I_sm_address_11_AP,
         dvm_I_sm_address_11_AR, dvm_I_sm_address_11_C,
         dvm_I_sm_address_11_D, dvm_I_sm_address_11_DIN,
         dvm_I_sm_address_11_Q, dvm_I_sm_address_11_Q_tF,
         dvm_I_sm_address_12_AP, dvm_I_sm_address_12_AR,
         dvm_I_sm_address_12_C, dvm_I_sm_address_12_DIN,
         dvm_I_sm_address_12_Q, dvm_I_sm_address_12_Q_tF,
         dvm_I_sm_address_12_T, dvm_I_sm_address_13_AP,
         dvm_I_sm_address_13_AR, dvm_I_sm_address_13_C,
         dvm_I_sm_address_13_DIN, dvm_I_sm_address_13_Q,
         dvm_I_sm_address_13_Q_tF, dvm_I_sm_address_13_T,
         dvm_I_sm_address_14_AP, dvm_I_sm_address_14_AR,
         dvm_I_sm_address_14_C, dvm_I_sm_address_14_D,
         dvm_I_sm_address_14_DIN, dvm_I_sm_address_14_Q,
         dvm_I_sm_address_14_Q_tF, dvm_I_sm_address_15_AP,
         dvm_I_sm_address_15_AR, dvm_I_sm_address_15_C,
         dvm_I_sm_address_15_D, dvm_I_sm_address_15_DIN,
         dvm_I_sm_address_15_Q, dvm_I_sm_address_15_Q_tF,
         dvm_I_sm_address_16_AP, dvm_I_sm_address_16_AR,
         dvm_I_sm_address_16_C, dvm_I_sm_address_16_DIN,
         dvm_I_sm_address_16_Q, dvm_I_sm_address_16_Q_tF,
         dvm_I_sm_address_16_T, dvm_I_sm_address_17_AP,
         dvm_I_sm_address_17_AR, dvm_I_sm_address_17_C,
         dvm_I_sm_address_17_DIN, dvm_I_sm_address_17_Q,
         dvm_I_sm_address_17_Q_tF, dvm_I_sm_address_17_T,
         dvm_I_sm_address_18_AP, dvm_I_sm_address_18_AR,
         dvm_I_sm_address_18_C, dvm_I_sm_address_18_D,
         dvm_I_sm_address_18_DIN, dvm_I_sm_address_18_Q,
         dvm_I_sm_address_18_Q_tF, dvm_I_sm_address_19_AP,
         dvm_I_sm_address_19_AR, dvm_I_sm_address_19_C,
         dvm_I_sm_address_19_D, dvm_I_sm_address_19_DIN,
         dvm_I_sm_address_19_Q, dvm_I_sm_address_19_Q_tF,
         dvm_I_sm_address_1_AP, dvm_I_sm_address_1_AR,