ep2c5q208.hier_info

以cyclone系列的EP2C5Q208为核心的实验板程序.包括流水灯,I2C存储器.SPI存储器,数码管,串口,LCD等

RESET => CountEnd~0.IN0
RESET => comb~1.IN0
GCLK => Count[2].CLK
GCLK => Count[1].CLK
GCLK => Count[0].CLK
GCLK => CLK.CLK
GCLK => Flag.CLK
GCLK => CountEnd[5].CLK
GCLK => CountEnd[4].CLK
GCLK => CountEnd[3].CLK
GCLK => CountEnd[2].CLK
GCLK => CountEnd[1].CLK
GCLK => CountEnd[0].CLK
GCLK => Count[3].CLK
KBDATA => spdata[8].DATAIN
KBDATA => spdata[7].DATAIN
KBDATA => spdata[6].DATAIN
KBDATA => spdata[5].DATAIN
KBDATA => spdata[4].DATAIN
KBDATA => spdata[3].DATAIN
KBDATA => spdata[2].DATAIN
KBDATA => spdata[1].DATAIN
KBCLK => Count~4.IN1
KBCLK => CountEnd~0.IN1
EOC <= EOC~0.DB_MAX_OUTPUT_PORT_TYPE
PDATA[0] <= spdata[1].DB_MAX_OUTPUT_PORT_TYPE
PDATA[1] <= spdata[2].DB_MAX_OUTPUT_PORT_TYPE
PDATA[2] <= spdata[3].DB_MAX_OUTPUT_PORT_TYPE
PDATA[3] <= spdata[4].DB_MAX_OUTPUT_PORT_TYPE
PDATA[4] <= spdata[5].DB_MAX_OUTPUT_PORT_TYPE
PDATA[5] <= spdata[6].DB_MAX_OUTPUT_PORT_TYPE
PDATA[6] <= spdata[7].DB_MAX_OUTPUT_PORT_TYPE
PDATA[7] <= spdata[8].DB_MAX_OUTPUT_PORT_TYPE


|EP2C5Q208|DS18B20:inst4
RESET => EOCtemp.LATCH_ENABLE
RESET => PDATA[6]~reg0.ACLR
RESET => PDATA[5]~reg0.ACLR
RESET => PDATA[4]~reg0.ACLR
RESET => PDATA[3]~reg0.ACLR
RESET => PDATA[2]~reg0.ACLR
RESET => PDATA[1]~reg0.ACLR
RESET => PDATA[0]~reg0.ACLR
RESET => CLKCNT[4].ACLR
RESET => PDATA[7]~reg0.ACLR
RESET => CLKCNT[3].ACLR
RESET => CLKCNT[2].ACLR
RESET => CLKCNT[1].ACLR
RESET => CLKCNT[0].ACLR
RESET => CLKCNT[5].ACLR
RESET => state[1].ACLR
RESET => state[0].ACLR
RESET => Count[4].ACLR
RESET => Count[3].ACLR
RESET => Count[2].ACLR
RESET => Count[1].ACLR
RESET => Count[0].ACLR
RESET => state[2].ACLR
RESET => DATA[11].ACLR
RESET => DATA[10].ACLR
RESET => DATA[9].ACLR
RESET => DATA[8].ACLR
RESET => DATA[7].ACLR
RESET => DATA[6].ACLR
RESET => DATA[5].ACLR
RESET => DATA[4].ACLR
CLK => CLKCNT[4].CLK
CLK => CLKCNT[3].CLK
CLK => CLKCNT[2].CLK
CLK => CLKCNT[1].CLK
CLK => CLKCNT[0].CLK
CLK => CLKCNT[5].CLK
Fresh => state~11.OUTPUTSELECT
Fresh => state~12.OUTPUTSELECT
Fresh => state~13.OUTPUTSELECT
DQ <= process2~0
EOC <= EOCtemp.DB_MAX_OUTPUT_PORT_TYPE
PDATA[0] <= PDATA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PDATA[1] <= PDATA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PDATA[2] <= PDATA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PDATA[3] <= PDATA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PDATA[4] <= PDATA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PDATA[5] <= PDATA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PDATA[6] <= PDATA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
PDATA[7] <= PDATA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|EP2C5Q208|I2C:inst8
RESET => comb~2.IN0
RESET => process9~0.IN1
RESET => process1~3.IN0
RESET => process1~4.IN0
RESET => process1~5.IN0
RESET => process1~0.IN0
RESET => STEP[2].OUTPUTSELECT
RESET => STEP[1].OUTPUTSELECT
RESET => STEP[0].OUTPUTSELECT
RESET => Count~0.IN0
RESET => comb~1.IN0
RESET => CLKSCL.PRESET
RESET => CLK100KHz.PRESET
RESET => process5~0.IN0
GCLK => Count[0].CLK
GCLK => \process2:Count[1].CLK
GCLK => \process2:Count[0].CLK
GCLK => \process3:Count[2].CLK
GCLK => \process3:Count[1].CLK
GCLK => \process3:Count[0].CLK
GCLK => Count[1].CLK
CLK => ~NO_FANOUT~
SCL <= process9~8.DB_MAX_OUTPUT_PORT_TYPE
SDA <= process9~10
I2C_CS => process1~0.IN1
I2C_RW => I2C_Data[7]$latch.LATCH_ENABLE
I2C_RW => process1_167.LATCH_ENABLE
I2C_RW => I2C_Data[6]$latch.LATCH_ENABLE
I2C_RW => I2C_Data[5]$latch.LATCH_ENABLE
I2C_RW => I2C_Data[4]$latch.LATCH_ENABLE
I2C_RW => I2C_Data[3]$latch.LATCH_ENABLE
I2C_RW => I2C_Data[2]$latch.LATCH_ENABLE
I2C_RW => I2C_Data[1]$latch.LATCH_ENABLE
I2C_RW => I2C_Data[0]$latch.LATCH_ENABLE
I2C_RW => FLAG.CLK
I2C_RW => process1~14.IN0
I2C_RW => Count~0.IN1
I2C_RW => process1~1.IN0
I2C_STRB => process1~1.IN1
I2C_Address[0] => Equal~1.IN3
I2C_Address[0] => Equal~2.IN3
I2C_Address[0] => Equal~3.IN3
I2C_Address[1] => Equal~1.IN2
I2C_Address[1] => Equal~2.IN2
I2C_Address[1] => Equal~3.IN2
I2C_Data[0] <= process1~13
I2C_Data[1] <= process1~12
I2C_Data[2] <= process1~11
I2C_Data[3] <= process1~10
I2C_Data[4] <= process1~9
I2C_Data[5] <= process1~8
I2C_Data[6] <= process1~7
I2C_Data[7] <= process1~6


|EP2C5Q208|SPI:inst16
RESET => comb~2.IN0
RESET => process1~0.IN0
RESET => Count~0.IN0
RESET => comb~1.IN0
RESET => process2~0.IN0
RESET => Temp.ACLR
GCLK => SCLK~0.DATAB
GCLK => \process3:Count[3].CLK
GCLK => \process3:Count[2].CLK
GCLK => \process3:Count[1].CLK
GCLK => \process3:Count[0].CLK
GCLK => MOSI~reg0.CLK
GCLK => SSEL~reg0.CLK
GCLK => CLKEnable.CLK
GCLK => DataOUT[15].CLK
GCLK => DataOUT[14].CLK
GCLK => DataOUT[13].CLK
GCLK => DataOUT[12].CLK
GCLK => DataOUT[11].CLK
GCLK => DataOUT[10].CLK
GCLK => DataOUT[9].CLK
GCLK => DataOUT[8].CLK
GCLK => DataOUT[7].CLK
GCLK => DataOUT[6].CLK
GCLK => DataOUT[5].CLK
GCLK => DataOUT[4].CLK
GCLK => DataOUT[3].CLK
GCLK => DataOUT[2].CLK
GCLK => DataOUT[1].CLK
GCLK => DataOUT[0].CLK
GCLK => \process3:Count[4].CLK
CLK => Count[0].CLK
CLK => Count[1].CLK
MISO => DataOUT[15].DATAIN
MISO => DataOUT[14].DATAIN
MISO => DataOUT[13].DATAIN
MISO => DataOUT[12].DATAIN
MISO => DataOUT[11].DATAIN
MISO => DataOUT[10].DATAIN
MISO => DataOUT[9].DATAIN
MISO => DataOUT[8].DATAIN
MISO => DataOUT[7].DATAIN
MISO => DataOUT[6].DATAIN
MISO => DataOUT[5].DATAIN
MISO => DataOUT[4].DATAIN
MISO => DataOUT[3].DATAIN
MISO => DataOUT[2].DATAIN
MISO => DataOUT[1].DATAIN
MISO => DataOUT[0].DATAIN
MOSI <= MOSI~reg0.DB_MAX_OUTPUT_PORT_TYPE
SCLK <= SCLK~0.DB_MAX_OUTPUT_PORT_TYPE
SSEL <= SSEL~reg0.DB_MAX_OUTPUT_PORT_TYPE
SPI_CS => process1~0.IN1
SPI_RW => process1_156.LATCH_ENABLE
SPI_RW => SPI_Data[14]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[13]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[12]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[11]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[10]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[9]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[8]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[7]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[6]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[5]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[4]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[3]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[2]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[1]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[0]$latch.LATCH_ENABLE
SPI_RW => SPI_Data[15]$latch.LATCH_ENABLE
SPI_RW => process1~17.IN0
SPI_RW => Temp.DATAIN
SPI_STRB => Count~0.IN1
SPI_STRB => process1~17.IN1
SPI_STRB => Temp.LATCH_ENABLE
SPI_Address[0] => Address[0].DATAIN
SPI_Address[1] => Address[1].DATAIN
SPI_Address[2] => Address[2].DATAIN
SPI_Address[3] => Address[3].DATAIN
SPI_Address[4] => Address[4].DATAIN
SPI_Address[5] => Address[5].DATAIN
SPI_Address[6] => Address[6].DATAIN
SPI_Address[7] => Address[7].DATAIN
SPI_Data[0] <= process1~16
SPI_Data[1] <= process1~15
SPI_Data[2] <= process1~14
SPI_Data[3] <= process1~13
SPI_Data[4] <= process1~12
SPI_Data[5] <= process1~11
SPI_Data[6] <= process1~10
SPI_Data[7] <= process1~9
SPI_Data[8] <= process1~8
SPI_Data[9] <= process1~7
SPI_Data[10] <= process1~6
SPI_Data[11] <= process1~5
SPI_Data[12] <= process1~4
SPI_Data[13] <= process1~3
SPI_Data[14] <= process1~2
SPI_Data[15] <= process1~1


|EP2C5Q208|VGA:inst10
RESET => Enable~0.OUTPUTSELECT
RESET => Hcnt[8].ACLR
RESET => Hcnt[7].ACLR
RESET => Hcnt[6].ACLR
RESET => Hcnt[5].ACLR
RESET => Hcnt[4].ACLR
RESET => Hcnt[3].ACLR
RESET => Hcnt[2].ACLR
RESET => Hcnt[1].ACLR
RESET => Hcnt[0].ACLR
RESET => HsyncB.PRESET
RESET => Hcnt[9].ACLR
RESET => VsyncB.PRESET
RESET => Vcnt[8].ACLR
RESET => Vcnt[7].ACLR
RESET => Vcnt[6].ACLR
RESET => Vcnt[5].ACLR
RESET => Vcnt[4].ACLR
RESET => Vcnt[3].ACLR
RESET => Vcnt[2].ACLR
RESET => Vcnt[1].ACLR
RESET => Vcnt[0].ACLR
RESET => Vcnt[9].ACLR
RESET => Count[1].ACLR
RESET => Count[0].ACLR
RESET => Count[2].ACLR
CLK => Hcnt[8].CLK
CLK => Hcnt[7].CLK
CLK => Hcnt[6].CLK
CLK => Hcnt[5].CLK
CLK => Hcnt[4].CLK
CLK => Hcnt[3].CLK
CLK => Hcnt[2].CLK
CLK => Hcnt[1].CLK
CLK => Hcnt[0].CLK
CLK => HsyncB.CLK
CLK => Enable.CLK
CLK => Hcnt[9].CLK
CLKTemp => Count[1].CLK
CLKTemp => Count[0].CLK
CLKTemp => Count[2].CLK
R[0] <= R~6.DB_MAX_OUTPUT_PORT_TYPE
R[1] <= R~5.DB_MAX_OUTPUT_PORT_TYPE
R[2] <= R~4.DB_MAX_OUTPUT_PORT_TYPE
R[3] <= R~3.DB_MAX_OUTPUT_PORT_TYPE
G[0] <= G~6.DB_MAX_OUTPUT_PORT_TYPE
G[1] <= G~5.DB_MAX_OUTPUT_PORT_TYPE
G[2] <= G~4.DB_MAX_OUTPUT_PORT_TYPE
G[3] <= G~3.DB_MAX_OUTPUT_PORT_TYPE
B[0] <= B~6.DB_MAX_OUTPUT_PORT_TYPE
B[1] <= B~5.DB_MAX_OUTPUT_PORT_TYPE
B[2] <= B~4.DB_MAX_OUTPUT_PORT_TYPE
B[3] <= B~3.DB_MAX_OUTPUT_PORT_TYPE
VS <= VsyncB.DB_MAX_OUTPUT_PORT_TYPE
HS <= HsyncB.DB_MAX_OUTPUT_PORT_TYPE


|EP2C5Q208|Music:inst9
RESET => process0~0.IN0
CLK => \GenSpkS:Count11[9].CLK
CLK => \GenSpkS:Count11[8].CLK
CLK => \GenSpkS:Count11[7].CLK
CLK => \GenSpkS:Count11[6].CLK
CLK => \GenSpkS:Count11[5].CLK
CLK => \GenSpkS:Count11[4].CLK
CLK => \GenSpkS:Count11[3].CLK
CLK => \GenSpkS:Count11[2].CLK
CLK => \GenSpkS:Count11[1].CLK
CLK => \GenSpkS:Count11[0].CLK
CLK => FullSpkS.CLK
CLK => \GenSpkS:Count11[10].CLK
CLK8Hz => Count[0].CLK
CLK8Hz => Counter[7].CLK
CLK8Hz => Counter[6].CLK
CLK8Hz => Counter[5].CLK
CLK8Hz => Counter[4].CLK
CLK8Hz => Counter[3].CLK
CLK8Hz => Counter[2].CLK
CLK8Hz => Counter[1].CLK
CLK8Hz => Counter[0].CLK
CLK8Hz => Count[1].CLK
Enable => comb~1.IN0
Enable => comb~2.IN0
BEEP <= \SpkOut:SpkS.DB_MAX_OUTPUT_PORT_TYPE
CLK1K => Buzzer.DATAB
Speak => process0~0.IN1


|EP2C5Q208|LED:inst5
RESET => RAM_ARRAY[0][2].ACLR
RESET => RAM_ARRAY[0][1].ACLR
RESET => RAM_ARRAY[0][0].ACLR
RESET => RAM_ARRAY[1][3].ACLR
RESET => RAM_ARRAY[1][2].ACLR
RESET => RAM_ARRAY[1][1].ACLR
RESET => RAM_ARRAY[1][0].ACLR
RESET => RAM_ARRAY[2][3].ACLR
RESET => RAM_ARRAY[2][2].ACLR
RESET => RAM_ARRAY[2][1].ACLR
RESET => RAM_ARRAY[2][0].ACLR
RESET => RAM_ARRAY[3][3].ACLR
RESET => RAM_ARRAY[3][2].ACLR
RESET => RAM_ARRAY[3][1].ACLR
RESET => RAM_ARRAY[3][0].ACLR
RESET => RAM_ARRAY[4][3].ACLR
RESET => RAM_ARRAY[4][2].ACLR
RESET => RAM_ARRAY[4][1].ACLR
RESET => RAM_ARRAY[4][0].ACLR
RESET => RAM_ARRAY[5][3].ACLR
RESET => RAM_ARRAY[5][2].ACLR
RESET => RAM_ARRAY[5][1].ACLR
RESET => RAM_ARRAY[5][0].ACLR
RESET => RAM_ARRAY[6][3].ACLR
RESET => RAM_ARRAY[6][2].ACLR
RESET => RAM_ARRAY[6][1].ACLR
RESET => RAM_ARRAY[6][0].ACLR
RESET => RAM_ARRAY[7][3].ACLR
RESET => RAM_ARRAY[7][2].ACLR
RESET => RAM_ARRAY[7][1].ACLR
RESET => RAM_ARRAY[7][0].ACLR
RESET => RAM_ARRAY[0][3].ACLR
ClockScan => Refresh[1].CLK
ClockScan => Refresh[0].CLK
ClockScan => Refresh[2].CLK
CLK1Hz => Segment~0.DATAB
LEDValue[0] => RAM_ARRAY[1][0].DATAIN
LEDValue[0] => RAM_ARRAY[2][0].DATAIN
LEDValue[0] => RAM_ARRAY[3][0].DATAIN
LEDValue[0] => RAM_ARRAY[4][0].DATAIN
LEDValue[0] => RAM_ARRAY[5][0].DATAIN
LEDValue[0] => RAM_ARRAY[6][0].DATAIN
LEDValue[0] => RAM_ARRAY[7][0].DATAIN
LEDValue[0] => RAM_ARRAY[0][0].DATAIN
LEDValue[1] => RAM_ARRAY[1][1].DATAIN
LEDValue[1] => RAM_ARRAY[2][1].DATAIN
LEDValue[1] => RAM_ARRAY[3][1].DATAIN
LEDValue[1] => RAM_ARRAY[4][1].DATAIN
LEDValue[1] => RAM_ARRAY[5][1].DATAIN
LEDValue[1] => RAM_ARRAY[6][1].DATAIN
LEDValue[1] => RAM_ARRAY[7][1].DATAIN
LEDValue[1] => RAM_ARRAY[0][1].DATAIN
LEDValue[2] => RAM_ARRAY[1][2].DATAIN
LEDValue[2] => RAM_ARRAY[2][2].DATAIN
LEDValue[2] => RAM_ARRAY[3][2].DATAIN
LEDValue[2] => RAM_ARRAY[4][2].DATAIN
LEDValue[2] => RAM_ARRAY[5][2].DATAIN
LEDValue[2] => RAM_ARRAY[6][2].DATAIN
LEDValue[2] => RAM_ARRAY[7][2].DATAIN
LEDValue[2] => RAM_ARRAY[0][2].DATAIN
LEDValue[3] => RAM_ARRAY[1][3].DATAIN
LEDValue[3] => RAM_ARRAY[2][3].DATAIN
LEDValue[3] => RAM_ARRAY[3][3].DATAIN
LEDValue[3] => RAM_ARRAY[4][3].DATAIN
LEDValue[3] => RAM_ARRAY[5][3].DATAIN
LEDValue[3] => RAM_ARRAY[6][3].DATAIN
LEDValue[3] => RAM_ARRAY[7][3].DATAIN
LEDValue[3] => RAM_ARRAY[0][3].DATAIN
DigitValue[0] => Decoder~0.IN2
DigitValue[1] => Decoder~0.IN1
DigitValue[2] => Decoder~0.IN0
LightValue[0] => Light[0].DATAIN
LightValue[1] => Light[1].DATAIN
LightValue[2] => Light[2].DATAIN
LightValue[3] => Light[3].DATAIN
LightValue[4] => Light[4].DATAIN
LightValue[5] => Light[5].DATAIN
LightValue[6] => Light[6].DATAIN
LightValue[7] => Light[7].DATAIN
Segment[0] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
Segment[1] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
Segment[2] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
Segment[3] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
Segment[4] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
Segment[5] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
Segment[6] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
Segment[7] <= Segment~0.DB_MAX_OUTPUT_PORT_TYPE
Digit[0] <= Refresh[0].DB_MAX_OUTPUT_PORT_TYPE
Digit[1] <= Refresh[1].DB_MAX_OUTPUT_PORT_TYPE
Digit[2] <= Refresh[2].DB_MAX_OUTPUT_PORT_TYPE
Light[0] <= LightValue[0].DB_MAX_OUTPUT_PORT_TYPE
Light[1] <= LightValue[1].DB_MAX_OUTPUT_PORT_TYPE
Light[2] <= LightValue[2].DB_MAX_OUTPUT_PORT_TYPE
Light[3] <= LightValue[3].DB_MAX_OUTPUT_PORT_TYPE
Light[4] <= LightValue[4].DB_MAX_OUTPUT_PORT_TYPE
Light[5] <= LightValue[5].DB_MAX_OUTPUT_PORT_TYPE
Light[6] <= LightValue[6].DB_MAX_OUTPUT_PORT_TYPE
Light[7] <= LightValue[7].DB_MAX_OUTPUT_PORT_TYPE


|EP2C5Q208|Light:inst11
Period1mS => Count[6].CLK
Period1mS => Count[5].CLK
Period1mS => Count[4].CLK
Period1mS => Count[3].CLK
Period1mS => Count[2].CLK
Period1mS => Count[1].CLK
Period1mS => Count[0].CLK
Period1mS => clk1.CLK
Period1mS => Count[7].CLK
light[0] <= light[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
light[1] <= light[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
light[2] <= light[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
light[3] <= light[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
light[4] <= light[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
light[5] <= light[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
light[6] <= light[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
light[7] <= light[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE