ep2c5q208.map.qmsg

以cyclone系列的EP2C5Q208为核心的实验板程序.包括流水灯,I2C存储器.SPI存储器,数码管,串口,LCD等

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_o9m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_o9m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_o9m " "Info: Found entity 1: altsyncram_o9m" {  } { { "db/altsyncram_o9m.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/altsyncram_o9m.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/quartus51/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus51/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "d:/program files/quartus51/libraries/megafunctions/lpm_divide.tdf" 116 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_6tf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_6tf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_6tf " "Info: Found entity 1: lpm_divide_6tf" {  } { { "db/lpm_divide_6tf.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/lpm_divide_6tf.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_mhg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_mhg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_mhg " "Info: Found entity 1: sign_div_unsign_mhg" {  } { { "db/sign_div_unsign_mhg.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/sign_div_unsign_mhg.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_3td.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_3td.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_3td " "Info: Found entity 1: alt_u_div_3td" {  } { { "db/alt_u_div_3td.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/alt_u_div_3td.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_6m8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_6m8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_6m8 " "Info: Found entity 1: add_sub_6m8" {  } { { "db/add_sub_6m8.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/add_sub_6m8.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_7m8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_7m8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_7m8 " "Info: Found entity 1: add_sub_7m8" {  } { { "db/add_sub_7m8.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/add_sub_7m8.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_8m8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_8m8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_8m8 " "Info: Found entity 1: add_sub_8m8" {  } { { "db/add_sub_8m8.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/add_sub_8m8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_9m8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_9m8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_9m8 " "Info: Found entity 1: add_sub_9m8" {  } { { "db/add_sub_9m8.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/add_sub_9m8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_am8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_am8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_am8 " "Info: Found entity 1: add_sub_am8" {  } { { "db/add_sub_am8.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/add_sub_am8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_8i8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_8i8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_8i8 " "Info: Found entity 1: add_sub_8i8" {  } { { "db/add_sub_8i8.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/add_sub_8i8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_dlf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_dlf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_dlf " "Info: Found entity 1: lpm_divide_dlf" {  } { { "db/lpm_divide_dlf.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/lpm_divide_dlf.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_qhg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_qhg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_qhg " "Info: Found entity 1: sign_div_unsign_qhg" {  } { { "db/sign_div_unsign_qhg.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/sign_div_unsign_qhg.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_btd.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_btd.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_btd " "Info: Found entity 1: alt_u_div_btd" {  } { { "db/alt_u_div_btd.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/alt_u_div_btd.tdf" 38 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_bm8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_bm8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_bm8 " "Info: Found entity 1: add_sub_bm8" {  } { { "db/add_sub_bm8.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/add_sub_bm8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_cm8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_cm8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_cm8 " "Info: Found entity 1: add_sub_cm8" {  } { { "db/add_sub_cm8.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/add_sub_cm8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_dm8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_dm8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_dm8 " "Info: Found entity 1: add_sub_dm8" {  } { { "db/add_sub_dm8.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/add_sub_dm8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ci8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ci8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ci8 " "Info: Found entity 1: add_sub_ci8" {  } { { "db/add_sub_ci8.tdf" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/db/add_sub_ci8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "9 " "Info: Ignored 9 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_CARRY_SUM" "9 " "Info: Ignored 9 CARRY_SUM buffer(s)" {  } {  } 0 0 "Ignored %1!d! CARRY_SUM buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Info" "IOPT_MLS_DUP_LATCH_INFO_HDR" "" "Info: Duplicate LATCH primitives merged into single LATCH primitive" { { "Info"