ep2c5q208.map.qmsg

以cyclone系列的EP2C5Q208为核心的实验板程序.包括流水灯,I2C存储器.SPI存储器,数码管,串口,LCD等

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "ColorB VGA.vhd(125) " "Info (10035): Verilog HDL or VHDL information at VGA.vhd(125): object \"ColorB\" declared but not used" {  } { { "VGA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/VGA.vhd" 125 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "VGA.vhd(222) " "Info (10425): VHDL Case Statement information at VGA.vhd(222): OTHERS choice is never selected" {  } { { "VGA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/VGA.vhd" 222 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Music Music:inst9 " "Info: Elaborating entity \"Music\" for hierarchy \"Music:inst9\"" {  } { { "EP2C5Q208.bdf" "inst9" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 584 1080 1200 744 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "CODE Music.vhd(43) " "Info (10035): Verilog HDL or VHDL information at Music.vhd(43): object \"CODE\" declared but not used" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 43 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "HIGH Music.vhd(45) " "Info (10035): Verilog HDL or VHDL information at Music.vhd(45): object \"HIGH\" declared but not used" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 45 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "Music.vhd(294) " "Info (10425): VHDL Case Statement information at Music.vhd(294): OTHERS choice is never selected" {  } { { "Music.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Music.vhd" 294 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED LED:inst5 " "Info: Elaborating entity \"LED\" for hierarchy \"LED:inst5\"" {  } { { "EP2C5Q208.bdf" "inst5" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 128 984 1184 288 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "LED.vhd(84) " "Info (10425): VHDL Case Statement information at LED.vhd(84): OTHERS choice is never selected" {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 84 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "RAM_ARRAY LED.vhd(94) " "Warning (10631): VHDL Process Statement warning at LED.vhd(94): signal or variable \"RAM_ARRAY\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"RAM_ARRAY\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "LED.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/LED.vhd" 94 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Light Light:inst11 " "Info: Elaborating entity \"Light\" for hierarchy \"Light:inst11\"" {  } { { "EP2C5Q208.bdf" "inst11" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { -72 648 800 24 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "I2C_DATA\[7\] " "Warning: Converting tri-state bus \"I2C_DATA\[7\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "I2C_DATA\[6\] " "Warning: Converting tri-state bus \"I2C_DATA\[6\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "I2C_DATA\[5\] " "Warning: Converting tri-state bus \"I2C_DATA\[5\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "I2C_DATA\[4\] " "Warning: Converting tri-state bus \"I2C_DATA\[4\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "I2C_DATA\[3\] " "Warning: Converting tri-state bus \"I2C_DATA\[3\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "I2C_DATA\[2\] " "Warning: Converting tri-state bus \"I2C_DATA\[2\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "I2C_DATA\[1\] " "Warning: Converting tri-state bus \"I2C_DATA\[1\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "I2C_DATA\[0\] " "Warning: Converting tri-state bus \"I2C_DATA\[0\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[15\] " "Warning: Converting tri-state bus \"SPID\[15\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[14\] " "Warning: Converting tri-state bus \"SPID\[14\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[13\] " "Warning: Converting tri-state bus \"SPID\[13\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[12\] " "Warning: Converting tri-state bus \"SPID\[12\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[11\] " "Warning: Converting tri-state bus \"SPID\[11\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[10\] " "Warning: Converting tri-state bus \"SPID\[10\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[9\] " "Warning: Converting tri-state bus \"SPID\[9\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[8\] " "Warning: Converting tri-state bus \"SPID\[8\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[7\] " "Warning: Converting tri-state bus \"SPID\[7\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[6\] " "Warning: Converting tri-state bus \"SPID\[6\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[5\] " "Warning: Converting tri-state bus \"SPID\[5\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[4\] " "Warning: Converting tri-state bus \"SPID\[4\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[3\] " "Warning: Converting tri-state bus \"SPID\[3\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[2\] " "Warning: Converting tri-state bus \"SPID\[2\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[1\] " "Warning: Converting tri-state bus \"SPID\[1\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "SPID\[0\] " "Warning: Converting tri-state bus \"SPID\[0\]\" that feeds logic into logic" {  } {  } 0 0 "Converting tri-state bus \"%1!s!\" that feeds logic into logic" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Operation:inst13\|SPI_Address\[3\] data_in GND " "Warning: Reduced register \"Operation:inst13\|SPI_Address\[3\]\" with stuck data_in port to stuck value GND" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 356 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Operation:inst13\|SPI_Address\[2\] data_in GND " "Warning: Reduced register \"Operation:inst13\|SPI_Address\[2\]\" with stuck data_in port to stuck value GND" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 356 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Operation:inst13\|SPI_Address\[1\] data_in GND " "Warning: Reduced register \"Operation:inst13\|SPI_Address\[1\]\" with stuck data_in port to stuck value GND" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 356 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Operation:inst13\|SPI_Address\[0\] data_in GND " "Warning: Reduced register \"Operation:inst13\|SPI_Address\[0\]\" with stuck data_in port to stuck value GND" {  } { { "Operation.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Operation.vhd" 356 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Light:inst11\|Count\[7\] Light:inst11\|clk1 " "Info: Duplicate register \"Light:inst11\|Count\[7\]\" merged to single register \"Light:inst11\|clk1\"" {  } { { "Light.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Light.vhd" 46 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "SPI:inst16\|CLKEnable SPI:inst16\|SSEL " "Info: Duplicate register \"SPI:inst16\|CLKEnable\" merged to single register \"SPI:inst16\|SSEL\"" {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 54 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Frequency:inst\|\\CLK1uS:Count\[5\] Frequency:inst\|Period1uS " "Info: Duplicate register \"Frequency:inst\|\\CLK1uS:Count\[5\]\" merged to single register \"Frequency:inst\|Period1uS\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Frequency:inst\|Period1mS Frequency:inst\|\\CLK1uS:Count1\[9\] " "Info: Duplicate register \"Frequency:inst\|Period1mS\" merged to single register \"Frequency:inst\|\\CLK1uS:Count1\[9\]\"" {  } { { "Frequency.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Frequency.vhd" 82 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Frequency:inst\|LCDCLK Frequency:inst\|\\CLK1uS:Count1\[8\] " "Info: Duplicate register \"Frequency:inst\|LCDCLK\" merged to single register \"Frequency:inst\|\\CLK1uS:Count1\[8\]\"" {  } { { "Frequency.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Frequency.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Frequency:inst\|RS232CLK Frequency:inst\|\\CLK1uS:Count3\[3\] " "Info: Duplicate register \"Frequency:inst\|RS232CLK\" merged to single register \"Frequency:inst\|\\CLK1uS:Count3\[3\]\"" {  } { { "Frequency.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Frequency.vhd" 34 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Frequency:inst\|irDACLK Frequency:inst\|\\CLK1uS:CountT\[4\] " "Info: Duplicate register \"Frequency:inst\|irDACLK\" merged to single register \"Frequency:inst\|\\CLK1uS:CountT\[4\]\"" {  } { { "Frequency.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Frequency.vhd" 35 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Frequency:inst\|Period1S Frequency:inst\|\\CLK1uS:Count2\[9\] " "Info: Duplicate register \"Frequency:inst\|Period1S\" merged to single register \"Frequency:inst\|\\CLK1uS:Count2\[9\]\"" {  } { { "Frequency.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Frequency.vhd" 111 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Frequency:inst\|CLK2Hz Frequency:inst\|\\CLK1uS:Count2\[8\] " "Info: Duplicate register \"Frequency:inst\|CLK2Hz\" merged to single register \"Frequency:inst\|\\CLK1uS:Count2\[8\]\"" {  } { { "Frequency.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Frequency.vhd" 38 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Frequency:inst\|CLK8Hz Frequency:inst\|\\CLK1uS:Count2\[7\] " "Info: Duplicate register \"Frequency:inst\|CLK8Hz\" merged to single register \"Frequency:inst\|\\CLK1uS:Count2\[7\]\"" {  } { { "Frequency.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/Frequency.vhd" 37 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "KeyBoard:inst3\|Mega_cnt\[0\] DS18B20:inst4\|CLKCNT\[0\] " "Info: Duplicate register \"KeyBoard:inst3\|Mega_cnt\[0\]\" merged to single register \"DS18B20:inst4\|CLKCNT\[0\]\"" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 35 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KeyBoard:inst3\|Mega_cnt\[1\] DS18B20:inst4\|CLKCNT\[1\] " "Info: Duplicate register \"KeyBoard:inst3\|Mega_cnt\[1\]\" merged to single register \"DS18B20:inst4\|CLKCNT\[1\]\"" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 35 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "KeyBoard:inst3\|Mega_cnt\[2\] DS18B20:inst4\|CLKCNT\[2\] " "Info: Duplicate register \"KeyBoard:inst3\|Mega_cnt\[2\]\" merged to single register \"DS18B20:inst4\|CLKCNT\[2\]\"" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 35 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KeyBoard:inst3\|Mega_cnt\[3\] DS18B20:inst4\|CLKCNT\[3\] " "Info: Duplicate register \"KeyBoard:inst3\|Mega_cnt\[3\]\" merged to single register \"DS18B20:inst4\|CLKCNT\[3\]\"" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 35 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KeyBoard:inst3\|Mega_cnt\[4\] DS18B20:inst4\|CLKCNT\[4\] " "Info: Duplicate register \"KeyBoard:inst3\|Mega_cnt\[4\]\" merged to single register \"DS18B20:inst4\|CLKCNT\[4\]\"" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 30 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KeyBoard:inst3\|Mega_cnt\[5\] DS18B20:inst4\|CLKCNT\[5\] " "Info: Duplicate register \"KeyBoard:inst3\|Mega_cnt\[5\]\" merged to single register \"DS18B20:inst4\|CLKCNT\[5\]\"" {  } { { "KeyBoard.v" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/KeyBoard.v" 35 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_ROM_FUNCTIONALITY_CHANGE_ALTSYNCRAM" "KeyBoard:inst3\|reduce_or~17 " "Warning: Created node \"KeyBoard:inst3\|reduce_or~17\" as a ROM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block. Power-up state differs from the original design." {  } {  } 0 0 "Created node \"%1!s!\" as a ROM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block. Power-up state differs from the original design." 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_ROM_INFERRED" "KeyBoard:inst3\|reduce_or~17 256 5 " "Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=256, WIDTH_A=5) from the following design logic: \"KeyBoard:inst3\|reduce_or~17\"" {  } {  } 0 0 "Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/program files/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}