ep2c5q208.map.qmsg

以cyclone系列的EP2C5Q208为核心的实验板程序.包括流水灯,I2C存储器.SPI存储器,数码管,串口,LCD等

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DS18B20 DS18B20:inst4 " "Info: Elaborating entity \"DS18B20\" for hierarchy \"DS18B20:inst4\"" {  } { { "EP2C5Q208.bdf" "inst4" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 472 56 208 568 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "EOCtemp DS18B20.vhd(203) " "Warning (10631): VHDL Process Statement warning at DS18B20.vhd(203): signal or variable \"EOCtemp\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"EOCtemp\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "DS18B20.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/DS18B20.vhd" 203 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C I2C:inst8 " "Info: Elaborating entity \"I2C\" for hierarchy \"I2C:inst8\"" {  } { { "EP2C5Q208.bdf" "inst8" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 696 520 736 856 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "SDAIN I2C.vhd(67) " "Info (10035): Verilog HDL or VHDL information at I2C.vhd(67): object \"SDAIN\" declared but not used" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 67 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "SDAOUT I2C.vhd(67) " "Info (10035): Verilog HDL or VHDL information at I2C.vhd(67): object \"SDAOUT\" declared but not used" {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 67 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "I2C_Data I2C.vhd(90) " "Warning (10631): VHDL Process Statement warning at I2C.vhd(90): signal or variable \"I2C_Data\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"I2C_Data\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "Value I2C.vhd(90) " "Warning (10631): VHDL Process Statement warning at I2C.vhd(90): signal or variable \"Value\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"Value\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "COMMAND I2C.vhd(90) " "Warning (10631): VHDL Process Statement warning at I2C.vhd(90): signal or variable \"COMMAND\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"COMMAND\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ADDRESS I2C.vhd(90) " "Warning (10631): VHDL Process Statement warning at I2C.vhd(90): signal or variable \"ADDRESS\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ADDRESS\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DATA I2C.vhd(90) " "Warning (10631): VHDL Process Statement warning at I2C.vhd(90): signal or variable \"DATA\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"DATA\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 90 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "Start I2C.vhd(173) " "Warning (10631): VHDL Process Statement warning at I2C.vhd(173): signal or variable \"Start\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"Start\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 173 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "SDA I2C.vhd(226) " "Warning (10631): VHDL Process Statement warning at I2C.vhd(226): signal or variable \"SDA\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"SDA\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 226 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DataOUT I2C.vhd(226) " "Warning (10631): VHDL Process Statement warning at I2C.vhd(226): signal or variable \"DataOUT\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"DataOUT\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "I2C.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/I2C.vhd" 226 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SPI SPI:inst16 " "Info: Elaborating entity \"SPI\" for hierarchy \"SPI:inst16\"" {  } { { "EP2C5Q208.bdf" "inst16" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 888 520 744 1080 "inst16" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "Temp SPI.vhd(59) " "Warning (10631): VHDL Process Statement warning at SPI.vhd(59): signal or variable \"Temp\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"Temp\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 59 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "SPI_Data SPI.vhd(84) " "Warning (10631): VHDL Process Statement warning at SPI.vhd(84): signal or variable \"SPI_Data\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"SPI_Data\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "Address SPI.vhd(84) " "Warning (10631): VHDL Process Statement warning at SPI.vhd(84): signal or variable \"Address\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"Address\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DataIN SPI.vhd(84) " "Warning (10631): VHDL Process Statement warning at SPI.vhd(84): signal or variable \"DataIN\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"DataIN\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "SPI.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/SPI.vhd" 84 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA VGA:inst10 " "Info: Elaborating entity \"VGA\" for hierarchy \"VGA:inst10\"" {  } { { "EP2C5Q208.bdf" "inst10" { Schematic "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/EP2C5Q208.bdf" { { 440 1064 1200 568 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "ColorR VGA.vhd(123) " "Info (10035): Verilog HDL or VHDL information at VGA.vhd(123): object \"ColorR\" declared but not used" {  } { { "VGA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/VGA.vhd" 123 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "ColorG VGA.vhd(124) " "Info (10035): Verilog HDL or VHDL information at VGA.vhd(124): object \"ColorG\" declared but not used" {  } { { "VGA.vhd" "" { Text "G:/My File/File/study/FPGA/Procedure/EP2C5Q208/VGA.vhd" 124 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}