superio_top_struct.vhd

Run Pac-man Game Based on 8086/8088 FPGA IP Core

-------------------------------------------------------------------------------
--                                                                           --
--  CPU86 - VHDL CPU8088 IP core                                             --
--  Copyright (C) 2005 HT-LAB                                                --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  This library is free software; you can redistribute it and/or            --
--  modify it under the terms of the GNU Lesser General Public               --
--  License as published by the Free Software Foundation; either             --
--  version 2.1 of the License, or (at your option) any later version.       --
--                                                                           --
--  This library is distributed in the hope that it will be useful,          --
--  but WITHOUT ANY WARRANTY; without even the implied warranty of           --
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        --
--  Lesser General Public License for more details.                          --
--                                                                           --
--  Full details of the license can be found in the file "copying.txt".      --
--                                                                           --
--  You should have received a copy of the GNU Lesser General Public         --
--  License along with this library; if not, write to the Free Software      --
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  --
--                                                                           --
-------------------------------------------------------------------------------
--
-- VHDL Architecture Super_IO.superio_top.symbol
--
-- Created: by - Hans 22/08/2005
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY superio_top IS
   GENERIC( 
      COM_DIVIDER   : integer := 15;
      TMR_DIVIDER91 : integer := 359256;
      UART2_G       : boolean := TRUE
   );
   PORT( 
      abus     : IN     std_logic_vector (15 DOWNTO 0);
      clk      : IN     std_logic;
      dbusin   : IN     std_logic_vector (7 DOWNTO 0);
      inport   : IN     std_logic_vector (7 DOWNTO 0);
      iom      : IN     std_logic;
      rdn      : IN     std_logic;
      resetn   : IN     std_logic;
      rx1      : IN     std_logic;
      rx2      : IN     std_logic;
      wrn      : IN     std_logic;
      dbusout  : OUT    std_logic_vector (7 DOWNTO 0);
      outport  : OUT    std_logic_vector (7 DOWNTO 0);
      pulse182 : OUT    std_logic;
      tx1      : OUT    std_logic;
      tx2      : OUT    std_logic
   );

-- Declarations

END superio_top ;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ARCHITECTURE struct OF superio_top IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL cspion     : std_logic;
   SIGNAL cstmrn     : std_logic;
   SIGNAL csuart1n   : std_logic;
   SIGNAL csuart2n   : std_logic;
   SIGNAL dbus_pio   : std_logic_vector(7 DOWNTO 0);
   SIGNAL dbus_tmr   : std_logic_vector(7 DOWNTO 0);
   SIGNAL dbus_uart1 : std_logic_vector(7 DOWNTO 0);
   SIGNAL dbus_uart2 : std_logic_vector(7 DOWNTO 0);
   SIGNAL sel_s      : std_logic_vector(3 DOWNTO 0);


   -- Component Declarations
   COMPONENT pio
   PORT (
      clk      : IN     std_logic ;
      cspion   : IN     std_logic ;
      dbusin   : IN     std_logic_vector (7 DOWNTO 0);
      inport   : IN     std_logic_vector (7 DOWNTO 0);
      resetn   : IN     std_logic ;
      wrn      : IN     std_logic ;
      dbus_pio : OUT    std_logic_vector (7 DOWNTO 0);
      outport  : OUT    std_logic_vector (7 DOWNTO 0)
   );
   END COMPONENT;
   COMPONENT timer_top
   GENERIC (
      DIVIDER_91HZ : integer := 359256
   );
   PORT (
      abus     : IN     std_logic ;
      clk      : IN     std_logic ;
      csn      : IN     std_logic ;
      dbus_in  : IN     std_logic_vector (7 DOWNTO 0);
      resetn   : IN     std_logic ;
      wrn      : IN     std_logic ;
      dbus_out : OUT    std_logic_vector (7 DOWNTO 0);
      pulse182 : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT uart
   GENERIC (
      DIVIDER : integer := 7
   );
   PORT (
      abus    : IN     std_logic_vector (1 DOWNTO 0);
      clk     : IN     std_logic ;
      csn     : IN     std_logic ;
      dbusin  : IN     std_logic_vector (7 DOWNTO 0);
      rdn     : IN     std_logic ;
      resetn  : IN     std_logic ;
      rx      : IN     std_logic ;
      wrn     : IN     std_logic ;
      dbusout : OUT    std_logic_vector (7 DOWNTO 0);
      tx      : OUT    std_logic 
   );
   END COMPONENT;

BEGIN
   -- Architecture concurrent statements
   -- HDL Embedded Text Block 4 dmux2
   -- dmux 1                                        
   --sel_s <= csuart1n & csuart2n & cspion & cstmrn;
   process(sel_s, dbus_uart1,dbus_uart2,dbus_pio,dbus_tmr)
      begin
         case sel_s is
              when "0111" => dbusout <= dbus_uart1;
              when "1011" => dbusout <= dbus_uart2;
              when "1101" => dbusout <= dbus_pio;
              when others => dbusout <= dbus_tmr;
          end case;         
   end process;

   -- HDL Embedded Text Block 7 chip_select2
   -- chip_select 4      
   
   -- cpu databus in multiplexer signal
   sel_s <= csuart1n & csuart2n & cspion & cstmrn;
   
   -- COM1, 0x03F8-0x03FF
   csuart1n <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
   
   -- COM2, 0x02F8-0x02FF
   csuart2n <= '0' when (abus(15 downto 3)="0000001011111" AND iom='1') else '1';
   
   -- PIO, 0x0398-0x039F
   cspion   <= '0' when (abus(15 downto 3)="0000001110011" AND iom='1') else '1';
                                 
   -- TMR, 0x0070, 0x0071
   cstmrn   <= '0' when (abus(15 downto 1)="000000000111000" AND iom='1') else '1';


   -- Instance port mappings.
   U_3 : pio
      PORT MAP (
         clk      => clk,
         cspion   => cspion,
         dbusin   => dbusin,
         inport   => inport,
         resetn   => resetn,
         wrn      => wrn,
         dbus_pio => dbus_pio,
         outport  => outport
      );
   U_2 : timer_top
      GENERIC MAP (
         DIVIDER_91HZ => TMR_DIVIDER91
      )
      PORT MAP (
         abus     => abus(0),
         clk      => clk,
         csn      => cstmrn,
         dbus_in  => dbusin,
         resetn   => resetn,
         wrn      => wrn,
         dbus_out => dbus_tmr,
         pulse182 => pulse182
      );
   U_1 : uart
      GENERIC MAP (
         DIVIDER => COM_DIVIDER
      )
      PORT MAP (
         abus    => abus(1 DOWNTO 0),
         clk     => clk,
         csn     => csuart1n,
         dbusin  => dbusin,
         rdn     => rdn,
         resetn  => resetn,
         rx      => rx1,
         wrn     => wrn,
         dbusout => dbus_uart1,
         tx      => tx1
      );

   g0: IF UART2_G GENERATE
   -- Optional embedded configurations
   FOR U_0 : uart USE ENTITY work.uart;

   BEGIN
      U_0 : uart
         GENERIC MAP (
            DIVIDER => COM_DIVIDER
         )
         PORT MAP (
            abus    => abus(1 DOWNTO 0),
            clk     => clk,
            csn     => csuart2n,
            dbusin  => dbusin,
            rdn     => rdn,
            resetn  => resetn,
            rx      => rx2,
            wrn     => wrn,
            dbusout => dbus_uart2,
            tx      => tx2
         );
   END GENERATE g0;

   g1: IF NOT UART2_G GENERATE
   BEGIN
      -- HDL Embedded Text Block 1 eb1
      -- eb1 1                          
      tx2<='1';
      dbus_uart2 <= (others => '0');              

   END GENERATE g1;

END struct;