timer_fsm_fsm.vhd

Run Pac-man Game Based on 8086/8088 FPGA IP Core

-------------------------------------------------------------------------------
--                                                                           --
--  CPU86 - VHDL CPU8088 IP core                                             --
--  Copyright (C) 2005 HT-LAB                                                --
--                                                                           --
--  Contact : mailto:[e-mail]                                        --
--  Web: http://www.ht-lab.com                                               --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  This library is free software; you can redistribute it and/or            --
--  modify it under the terms of the GNU Lesser General Public               --
--  License as published by the Free Software Foundation; either             --
--  version 2.1 of the License, or (at your option) any later version.       --
--                                                                           --
--  This library is distributed in the hope that it will be useful,          --
--  but WITHOUT ANY WARRANTY; without even the implied warranty of           --
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        --
--  Lesser General Public License for more details.                          --
--                                                                           --
--  Full details of the license can be found in the file "copying.txt".      --
--                                                                           --
--  You should have received a copy of the GNU Lesser General Public         --
--  License along with this library; if not, write to the Free Software      --
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  --
--                                                                           --
-------------------------------------------------------------------------------
--
-- VHDL Architecture Timer.Timer_fsm.interface
--
-- Created: by - Hans 21/08/2005
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY Timer_fsm IS
   PORT( 
      clk          : IN     std_logic;
      dbus_in      : IN     std_logic_vector (7 DOWNTO 0);
      leap_years_s : IN     std_logic;
      pulse1sec_s  : IN     std_logic;
      regsel_s     : IN     std_logic_vector (3 DOWNTO 0);
      resetn       : IN     std_logic;
      wr_s         : IN     std_logic;
      date         : OUT    std_logic_vector (5 DOWNTO 0);
      hours        : OUT    std_logic_vector (4 DOWNTO 0);
      minutes      : OUT    std_logic_vector (5 DOWNTO 0);
      months       : OUT    std_logic_vector (3 DOWNTO 0);
      seconds      : OUT    std_logic_vector (5 DOWNTO 0);
      years        : OUT    std_logic_vector (4 DOWNTO 0)
   );

-- Declarations

END Timer_fsm ;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
 
ARCHITECTURE fsm OF Timer_fsm IS

   TYPE STATE_TYPE IS (
      s0,
      s2,
      s3,
      s4,
      s5,
      s6,
      s7,
      s8
   );
 
   -- State vector declaration
   ATTRIBUTE state_vector : string;
   ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state";

   -- Declare current and next state signals
   SIGNAL current_state : STATE_TYPE;
   SIGNAL next_state : STATE_TYPE;

   -- Declare any pre-registered internal signals
   SIGNAL date_cld : std_logic_vector (5 DOWNTO 0);
   SIGNAL hours_cld : std_logic_vector (4 DOWNTO 0);
   SIGNAL minutes_cld : std_logic_vector (5 DOWNTO 0);
   SIGNAL months_cld : std_logic_vector (3 DOWNTO 0);
   SIGNAL seconds_cld : std_logic_vector (5 DOWNTO 0);
   SIGNAL years_cld : std_logic_vector (4 DOWNTO 0);

BEGIN

   -----------------------------------------------------------------
   clocked_proc : PROCESS ( 
      clk,
      resetn
   )
   -----------------------------------------------------------------
   BEGIN
      IF (resetn = '0') THEN
         current_state <= s0;
         -- Default Reset Values
         date_cld <= "011011";
         hours_cld <= "01011";
         minutes_cld <= "011110";
         months_cld <= "0111";
         seconds_cld <= "111010";
         years_cld <= "00101";
      ELSIF (clk'EVENT AND clk = '1') THEN
         current_state <= next_state;

         -- Combined Actions
         CASE current_state IS
            WHEN s2 => 
               if wr_s='1' then
               case regsel_s is
                when "0000" => seconds_cld <= dbus_in(5 downto 0);
                when "0010" => minutes_cld <= dbus_in(5 downto 0);
                when "0100" => hours_cld <= dbus_in(4 downto 0);
                when "0111" => date_cld <= dbus_in(5 downto 0);
                when "1000" => months_cld <= dbus_in(3 downto 0);
                when "1001" => years_cld <= dbus_in(4 downto 0);
                when others => years_cld <= years_cld;
               end case;
               end if;
            WHEN s3 => 
               seconds_cld<=seconds_cld+'1';
            WHEN s4 => 
               seconds_cld<=(others => '0');
               minutes_cld<= minutes_cld+'1';
            WHEN s5 => 
               minutes_cld<=(others=>'0');
               hours_cld<=hours_cld+'1';
            WHEN s6 => 
               hours_cld<=(others=>'0');
               date_cld<=date_cld+'1';
            WHEN s7 => 
               date_cld<="000001";
               months_cld<=months_cld+'1';
            WHEN s8 => 
               months_cld<="0001";
               years_cld<=years_cld+'1';
            WHEN OTHERS =>
               NULL;
         END CASE;
      END IF;
   END PROCESS clocked_proc;
 
   -----------------------------------------------------------------
   nextstate_proc : PROCESS ( 
      current_state,
      date_cld,
      hours_cld,
      leap_years_s,
      minutes_cld,
      months_cld,
      pulse1sec_s,
      seconds_cld,
      wr_s
   )
   -----------------------------------------------------------------
   BEGIN
      CASE current_state IS
         WHEN s0 => 
            IF (pulse1sec_s='1') THEN 
               next_state <= s3;
            ELSIF (wr_s='1' ) THEN 
               next_state <= s2;
            ELSE
               next_state <= s0;
            END IF;
         WHEN s2 => 
            IF (wr_s='0') THEN 
               next_state <= s0;
            ELSE
               next_state <= s2;
            END IF;
         WHEN s3 => 
            IF (seconds_cld="111011") THEN 
               next_state <= s4;
            ELSE
               next_state <= s0;
            END IF;
         WHEN s4 => 
            IF (minutes_cld="111011") THEN 
               next_state <= s5;
            ELSE
               next_state <= s0;
            END IF;
         WHEN s5 => 
            IF (hours_cld="10111") THEN 
               next_state <= s6;
            ELSE
               next_state <= s0;
            END IF;
         WHEN s6 => 
            IF (date_cld="011111") THEN 
               next_state <= s7;
            ELSIF (date_cld="011110" AND (months_cld="0100" OR months_cld="0110"
                   OR months_cld="1001" OR months_cld="1011")) THEN 
               next_state <= s7;
            ELSIF (date_cld="011101") THEN 
               next_state <= s7;
            ELSIF (date_cld="011101") THEN 
               next_state <= s0;
            ELSIF (date_cld="011100" AND months_cld="0010" 
                   AND leap_years_s='0') THEN 
               next_state <= s7;
            ELSE
               next_state <= s0;
            END IF;
         WHEN s7 => 
            IF (months_cld="1100") THEN 
               next_state <= s8;
            ELSE
               next_state <= s0;
            END IF;
         WHEN s8 => 
            next_state <= s0;
         WHEN OTHERS =>
            next_state <= s0;
      END CASE;
   END PROCESS nextstate_proc;
 
   -- Concurrent Statements
   -- Clocked output assignments
   date <= date_cld;
   hours <= hours_cld;
   minutes <= minutes_cld;
   months <= months_cld;
   seconds <= seconds_cld;
   years <= years_cld;
END fsm;