fft.v

jpeg压缩中离散余弦变换DCT快速算法代码

module butterfly(out1_re,out1_im,out2_re,out2_im,in1_re,in1_im,in2_re,in2_im,clk);
output[7:0] out1_re,out1_im,out2_re,out2_im;
input[7:0] in1_re,in1_im,in2_re,in2_im;
input clk;
reg[7:0] out1_re,out1_im,out2_re,out2_im;
reg[15:0] temp_re,temp_im;
reg[7:0] temp1,temp2;
    
function[15:0] mul;
input[7:0]    in;
reg[13:0]  str1;
reg[11:0]  str2;
reg[10:0]  str3;
reg[9:0]   str4;
reg[15:0]  mul1,mul2;

begin
   assign str4=in<<1;
   assign str3=str4<<2;
   assign str2=str3<<1;
   assign str1=str2<<2;
   assign mul1=str4+str3;
   assign mul2=str1+str2;
   mul=mul1+mul2;
end
endfunction 

always @(posedge clk)   
  begin
      temp_re=mul(in2_re);
      temp_im=mul(in2_im);
      temp1=temp_re[14:7]-temp_im[14:7];
      temp2=temp_re[14:7]+temp_im[14:7];
      out1_re=in1_re+temp1;
      out1_im=in1_im+temp1;
      out2_re=in2_re-temp2;
      out2_im=in2_im-temp2;
  end
  endmodule


/********************************************************************
        butterfly testbench
********************************************************************/
`timescale 1ns/100ps

`define   CLK_PERIOD   8

module butterfly_tb;
    
//===================================================================
reg   [7:0] in1_re;
reg   [7:0] in1_im;
reg   [7:0] in2_re;   
reg   [7:0] in2_im;
reg   clk;

//===================================================================
// ------------------------------------------------------------------
//
// CLOCK generator 
//
// ------------------------------------------------------------------
initial
begin: clock_generator
    clk = 1'b1;
    forever #(`CLK_PERIOD/2) clk=~clk;
end //clock generator

// ------------------------------------------------------------------
//
// input data generator 
//
// ------------------------------------------------------------------
always @(posedge clk)
begin
    in1_re   <= 8'h24;
    in1_im   <= 0;
    in2_re   <= 8'h17;
    in2_im   <= 0;
end

//===================================================================
butterfly butterfly(.out1_re(out1_re),
                    .out1_im(out1_im),
                    .out2_re(out2_re),
                    .out2_im(out2_im),
                    .in1_re(in1_re),
                    .in1_im(in1_im),
                    .in2_re(in2_re),
                    .in2_im(in2_im),
                    .clk(clk)            
                    );
//==============================================================================
//==============================================================================
//==============================================================================
endmodule