avalon_slave_if.v

Altera的基于NIOS II的LCD控制器源代码

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/*
 Avalon Slave Interface
 Implements control, address and count registesr.
 Peripheral controlled wait states to allow for different clock domains
 Registers in pixel clock domain, assumed to have 0 wait states.
 Registers required to support
- layer_X_on (control_reg)

VGA Timing
- PinP for layer1-4

Pixel Engine
- layer_X constant alpha
- Background value

Avalon master, one each for each master
- DMA start address
- DMA length
- DMA enable (to be set prior to enabling the layer to allow DMA to pre-fill the FIFO
- DMA active length - to be used with the windowing function
- DMA active start - to be used with the windowing function

Status registers, in addition to readback of value set above
- DMA FIFO Underflow
- DMA FIFO Overflow
- others?

Interrupts?
*/

module avalon_slave_if (
  reset_n,
  pixel_clk,
  clk_av,  //Avalon clock
//Avalon Slave Interface
  s_address,
  s_chipselect,
  s_read_n,
  s_write_n,
  s_writedata,
  s_waitrequest,
  s_readdata,
  int,
//Outputs to rest of LCD Controller
  const_alpha_lay1,
  const_alpha_lay2,
  const_alpha_lay3,
  const_alpha_lay4,
  background,
  layer_0_on,
  layer_1_on,
  layer_2_on,
  layer_3_on,
  layer_4_on,
  win_l1_h_start,
  win_l1_h_stop,
  win_l1_v_start,
  win_l1_v_stop,
  win_l2_h_start,
  win_l2_h_stop,
  win_l2_v_start,
  win_l2_v_stop,
  win_l3_h_start,
  win_l3_h_stop,
  win_l3_v_start,
  win_l3_v_stop,
  win_l4_h_start,
  win_l4_h_stop,
  win_l4_v_start,
  win_l4_v_stop,
  layer_0_dma_start_addr,
  layer_0_dma_length,
  layer_1_dma_start_addr,
  layer_1_dma_length,
  layer_2_dma_start_addr,
  layer_2_dma_length,
  layer_3_dma_start_addr,
  layer_3_dma_length,
  layer_4_dma_start_addr,
  layer_4_dma_length,
  dma_layer_0_on,
  dma_layer_1_on,
  dma_layer_2_on,
  dma_layer_3_on,
  dma_layer_4_on,
  vblank,
  end_of_picture
);

input reset_n;
input pixel_clk;
input clk_av;
input vblank;
input end_of_picture;

// Avalon DMA register slave
input [5:0] s_address;
input s_chipselect;
input s_read_n;
input s_write_n;
input [31:0] s_writedata;
output s_waitrequest;
output [31:0] s_readdata;
output int; //interrupt output

//Outputs to LCD Controller
output [5:0] const_alpha_lay1;
output [5:0] const_alpha_lay2;
output [5:0] const_alpha_lay3;
output [5:0] const_alpha_lay4;
output [15:0] background;
output layer_0_on;
output layer_1_on;
output layer_2_on;
output layer_3_on;
output layer_4_on;
output [11:0] win_l1_h_start;
output [11:0] win_l1_h_stop;
output [11:0] win_l1_v_start;
output [11:0] win_l1_v_stop;
output [11:0] win_l2_h_start;
output [11:0] win_l2_h_stop;
output [11:0] win_l2_v_start;
output [11:0] win_l2_v_stop;
output [11:0] win_l3_h_start;
output [11:0] win_l3_h_stop;
output [11:0] win_l3_v_start;
output [11:0] win_l3_v_stop;
output [11:0] win_l4_h_start;
output [11:0] win_l4_h_stop;
output [11:0] win_l4_v_start;
output [11:0] win_l4_v_stop;

output [31:0] layer_0_dma_start_addr;
output [31:0] layer_0_dma_length;
output [31:0] layer_1_dma_start_addr;
output [31:0] layer_1_dma_length;
output [31:0] layer_2_dma_start_addr;
output [31:0] layer_2_dma_length;
output [31:0] layer_3_dma_start_addr;
output [31:0] layer_3_dma_length;
output [31:0] layer_4_dma_start_addr;
output [31:0] layer_4_dma_length;
output dma_layer_0_on;
output dma_layer_1_on;
output dma_layer_2_on;
output dma_layer_3_on;
output dma_layer_4_on;


reg [4:0] control_reg;
reg [5:0] const_alpha_lay1_reg;
reg [5:0] const_alpha_lay2_reg;
reg [5:0] const_alpha_lay3_reg;
reg [5:0] const_alpha_lay4_reg;
reg [15:0] background_reg;
reg [11:0] win_l1_h_start_reg;
reg [11:0] win_l1_h_stop_reg;
reg [11:0] win_l1_v_start_reg;
reg [11:0] win_l1_v_stop_reg;
reg [11:0] win_l2_h_start_reg;
reg [11:0] win_l2_h_stop_reg;
reg [11:0] win_l2_v_start_reg;
reg [11:0] win_l2_v_stop_reg;
reg [11:0] win_l3_h_start_reg;
reg [11:0] win_l3_h_stop_reg;
reg [11:0] win_l3_v_start_reg;
reg [11:0] win_l3_v_stop_reg;
reg [11:0] win_l4_h_start_reg;
reg [11:0] win_l4_h_stop_reg;
reg [11:0] win_l4_v_start_reg;
reg [11:0] win_l4_v_stop_reg;

reg [31:0] layer_0_dma_start_addr_reg;
reg [31:0] layer_0_dma_length_reg;
reg [31:0] layer_1_dma_start_addr_reg;
reg [31:0] layer_1_dma_length_reg;
reg [31:0] layer_2_dma_start_addr_reg;
reg [31:0] layer_2_dma_length_reg;
reg [31:0] layer_3_dma_start_addr_reg;
reg [31:0] layer_3_dma_length_reg;
reg [31:0] layer_4_dma_start_addr_reg;
reg [31:0] layer_4_dma_length_reg;
reg [4:0] dma_control_reg;
reg [31:0] status_reg;
reg int_enable_reg;
reg int_clear_reg;
reg int_status_reg;

reg int;

reg [31:0] 	s_readdata;

// s_waitrequest generation - START
// synchronistion across clock boundary
reg s_waitrequest; //avalon clock domain
wire waitrequest_off; //avalon clock domain
reg waitrequest_pclk_1; //pixel clock domain
reg waitrequest_pclk_2; //pixel clock domain
reg waitrequest_avclk_1; //avalon clock domain
reg waitrequest_avclk_2; //avalon clock domain

always @(s_chipselect or waitrequest_off)
 if (s_chipselect & ~waitrequest_off)
  s_waitrequest = 1'b1; //insert wait states
 else if (s_chipselect & waitrequest_off)
  s_waitrequest = 1'b0; //transfer complete
 else
  s_waitrequest = 1'b0;
  
//sync waitrequest to pixel clock domain
always @(posedge pixel_clk or posedge waitrequest_off)
 if (waitrequest_off)
  begin
   waitrequest_pclk_1 <= 1'b0;
   waitrequest_pclk_2 <= 1'b0;
  end
 else
  begin
   waitrequest_pclk_1 <= s_waitrequest;
   waitrequest_pclk_2 <= waitrequest_pclk_1;
  end

//sync waitrequest_pclk_2 to avalon clock domain
always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  begin
   waitrequest_avclk_1 <= 1'b0;
   waitrequest_avclk_1 <= 1'b0;
  end
 else if (waitrequest_off)
  begin
   waitrequest_avclk_1 <= 1'b0;
   waitrequest_avclk_2 <= 1'b0;
  end
 else
  begin
   waitrequest_avclk_1 <= waitrequest_pclk_2;
   waitrequest_avclk_2 <= waitrequest_avclk_1;
  end

assign waitrequest_off = waitrequest_avclk_1 & waitrequest_avclk_2;

// s_waitrequest generation - END

//Interrupt generation
always @(end_of_picture or int_clear_reg or int_enable_reg or reset_n)
 if (~reset_n || int_clear_reg)
  int <= 0;
 else if (end_of_picture && int_enable_reg)
  int <= 1; //set interrupt only if enabled


//add register for int_status, int_clear, int_enable


always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  int_enable_reg <= 1'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd33))
  int_enable_reg <= s_writedata[0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  int_clear_reg <= 1'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd34))
  int_clear_reg <= s_writedata[0];
 else
  int_clear_reg <= 1'b0;

always @(int)
  int_status_reg <= int;
  

//Register Bank - START
always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  control_reg <= 5'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd00))
  control_reg <= s_writedata[4:0];

assign layer_0_on = control_reg[0];
assign layer_1_on = control_reg[1];
assign layer_2_on = control_reg[2];
assign layer_3_on = control_reg[3];
assign layer_4_on = control_reg[4];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  const_alpha_lay1_reg <= 6'b0;
 else if (s_chipselect & ~s_write_n & (s_address == 6'd01))
  const_alpha_lay1_reg <= s_writedata[5:0];

assign const_alpha_lay1 = const_alpha_lay1_reg[5:0];

always @(posedge clk_av or negedge reset_n)
 if (~reset_n)
  const_alpha_lay2_reg <= 6'b0;