vga_timing.v

Altera的基于NIOS II的LCD控制器源代码

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module vga_timing ( 
// inputs
	reset,
	vga_clk,
	R_in,
	G_in,
	B_in,
	win_l1_h_start,
	win_l1_h_stop,
	win_l1_v_start,
	win_l1_v_stop,
	win_l2_h_start,
	win_l2_h_stop,
	win_l2_v_start,
	win_l2_v_stop,
	win_l3_h_start,
	win_l3_h_stop,
	win_l3_v_start,
	win_l3_v_stop,
	win_l4_h_start,
	win_l4_h_stop,
	win_l4_v_start,
	win_l4_v_stop,
//outputs
	hsync,
	vsync,
	sync,
	blank,
	R,
	G,
	B,
	read_next_pixel,
	end_of_picture,
	act_l0,
	act_l1,
	act_l2,
	act_l3,
	act_l4,
	vblank
);
//inputs
input reset;
input vga_clk;
input [5:0] R_in;
input [5:0] G_in;
input [5:0] B_in;

//PinP variable inputs, from register interface
//PinP supported by layers 1-4 NOT layer0.
input [11:0] win_l1_h_start;
input [11:0] win_l1_h_stop;
input [11:0] win_l1_v_start;
input [11:0] win_l1_v_stop;

input [11:0] win_l2_h_start;
input [11:0] win_l2_h_stop;
input [11:0] win_l2_v_start;
input [11:0] win_l2_v_stop;

input [11:0] win_l3_h_start;
input [11:0] win_l3_h_stop;
input [11:0] win_l3_v_start;
input [11:0] win_l3_v_stop;

input [11:0] win_l4_h_start;
input [11:0] win_l4_h_stop;
input [11:0] win_l4_v_start;
input [11:0] win_l4_v_stop;

//outputs
output hsync;
output vsync;
output sync;
output blank;
output [5:0] R;
output [5:0] G;
output [5:0] B;
output read_next_pixel;
output end_of_picture;
output vblank;

//act_lx outputs valid when data to be read from DMA-FIFO's
output act_l0;
output act_l1;
output act_l2;
output act_l3;
output act_l4;


wire hsync;
wire vsync;
wire sync;
wire blank;

wire [5:0] R;
wire [5:0] G;
wire [5:0] B;
wire read_next_pixel;
wire end_of_picture;
wire active;

reg [10:0] pix_count;
reg [10:0] line_count;
wire hblank;
wire vblank;

//pipeline delay
//this value is the pipeline delay thruogh the pixel_engine & fifo's
parameter pipeline_delay_l0 = 5;
parameter pipeline_delay_l1 = 5;
parameter pipeline_delay_l2 = 5;
parameter pipeline_delay_l3 = 4;
parameter pipeline_delay_l4 = 3;

// 640 by 480 VGA timing parameters
// horizontal timing parameters
parameter hsync_end = 96;  //sync pulse, 640x480 = 96
parameter hblank_begin = 144;  // = sync + back porch, 640x480 = 144
parameter hblank_end = 784;  // = sync + back porch + h_resolution, 640x480 = 784
parameter hline_end = 800;  // = sync + back porch + h_resolution + front porch, 640x480 = 800

// vertical timing parameters
parameter vsync_end = 2;  //sync pulse, 640x480 = 2
parameter vblank_begin = 33;  // = sync + back porch, 640x480 = 33
parameter vblank_end = 513;  // = sync + back porch + v_resolution, 640x480 = 513
parameter vframe_end = 524;  // = sync + back porch + v_resolution + front porch, 640x480 = 524

// these are all the syncs and blanks for the video timing
assign hsync = (pix_count < hsync_end) ? 1'b0 : 1'b1;
assign vsync = (line_count < vsync_end) ? 1'b0 : 1'b1;
assign hblank = ((pix_count > (hblank_begin-1)) && (pix_count < (hblank_end))) ? 1'b1 : 1'b0;
assign vblank = ((line_count > (vblank_begin-1)) && (line_count < (vblank_end))) ? 1'b1 : 1'b0;
assign sync = vsync & hsync;
assign blank = vblank & hblank;

// active indicates that the color value should be output, or black when not active
assign active = ((line_count > (vblank_begin-1)) && (line_count < (vblank_end)) && (pix_count > (hblank_begin - 1)) && (pix_count < (hblank_end))) ? 1'b1 : 1'b0;

// act_lx indicates that data should be read from the appropriate DMA-FIFO
//Layer0 does not have PinP functionality
//Layer1-4 have PinP functionality
wire [11:0] l1_vblank_end;
wire [11:0] l2_vblank_end;
wire [11:0] l3_vblank_end;
wire [11:0] l4_vblank_end;
assign l1_vblank_end = win_l1_v_stop == 'b0 ? 'b0 :  (vblank_end - vblank_begin - win_l1_v_stop);
assign l2_vblank_end = win_l2_v_stop == 'b0 ? 'b0 :  (vblank_end - vblank_begin - win_l2_v_stop);
assign l3_vblank_end = win_l3_v_stop == 'b0 ? 'b0 :  (vblank_end - vblank_begin - win_l3_v_stop);
assign l4_vblank_end = win_l4_v_stop == 'b0 ? 'b0 :  (vblank_end - vblank_begin - win_l4_v_stop);

wire [11:0] l1_hblank_end;
wire [11:0] l2_hblank_end;
wire [11:0] l3_hblank_end;
wire [11:0] l4_hblank_end;
assign l1_hblank_end = win_l1_h_stop == 'b0 ? 'b0 :  (hblank_end - hblank_begin - win_l1_h_stop);
assign l2_hblank_end = win_l2_h_stop == 'b0 ? 'b0 :  (hblank_end - hblank_begin - win_l2_h_stop);
assign l3_hblank_end = win_l3_h_stop == 'b0 ? 'b0 :  (hblank_end - hblank_begin - win_l3_h_stop);
assign l4_hblank_end = win_l4_h_stop == 'b0 ? 'b0 :  (hblank_end - hblank_begin - win_l4_h_stop);

assign act_l0 = ((line_count > (vblank_begin - 1)) && (line_count < (vblank_end)) && (pix_count > (hblank_begin - 1 - pipeline_delay_l0)) && (pix_count < (hblank_end - pipeline_delay_l0))) ? 1'b1 : 1'b0;
assign act_l1 = ((line_count > (vblank_begin - 1 + win_l1_v_start)) && (line_count < (vblank_end - l1_vblank_end)) && (pix_count > (hblank_begin - 1 - pipeline_delay_l1 + win_l1_h_start)) && (pix_count < (hblank_end - pipeline_delay_l1 - l1_hblank_end))) ? 1'b1 : 1'b0;
assign act_l2 = ((line_count > (vblank_begin - 1 + win_l2_v_start)) && (line_count < (vblank_end - l2_vblank_end)) && (pix_count > (hblank_begin - 1 - pipeline_delay_l2 + win_l2_h_start)) && (pix_count < (hblank_end - pipeline_delay_l2 - l2_hblank_end))) ? 1'b1 : 1'b0;
assign act_l3 = ((line_count > (vblank_begin - 1 + win_l3_v_start)) && (line_count < (vblank_end - l3_vblank_end)) && (pix_count > (hblank_begin - 1 - pipeline_delay_l3 + win_l3_h_start)) && (pix_count < (hblank_end - pipeline_delay_l3 - l3_hblank_end))) ? 1'b1 : 1'b0;
assign act_l4 = ((line_count > (vblank_begin - 1 + win_l4_v_start)) && (line_count < (vblank_end - l4_vblank_end)) && (pix_count > (hblank_begin - 1 - pipeline_delay_l4 + win_l4_h_start)) && (pix_count < (hblank_end - pipeline_delay_l4 - l4_hblank_end))) ? 1'b1 : 1'b0;

// read_next_pixel asserts one clock before the next pixel value is needed
assign read_next_pixel = ((line_count > (vblank_begin-1)) && (line_count < (vblank_end)) && (pix_count > (hblank_begin - 2)) && (pix_count < (hblank_end - 1))) ? 1'b1 : 1'b0;

// end_of_picture asserts when the last pixel of a frame is displayed on the monitor
assign end_of_picture = ((pix_count == hblank_end) && (line_count == vblank_end - 1)) ? 1'b1 : 1'b0;

assign R = (active) ? R_in : 6'h00;		// red color value output to video DAC
assign G = (active) ? G_in : 6'h00;		// green color value output to video DAC
assign B = (active) ? B_in : 6'h00;		// blue color value output to video DAC


// the heart of the time base are these two counters, the pixel and line counters
always @ (posedge vga_clk or posedge reset)
begin
	if ( reset == 1'b1 )
	begin
		pix_count <= 11'h0;
		line_count <= 11'h0;
	end
	else
	begin
		if(pix_count == (hline_end-1))
		begin
			pix_count <= 11'h0;
			if(line_count == (vframe_end-1))
			begin
				line_count <= 11'h0;
			end
			else
			begin
				line_count <= line_count + 1'b1;
			end
		end
		else
		begin
			pix_count <= pix_count + 1'b1;
		end
	end
end

endmodule