📄 blender.v
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// ================================================================================
// (c) 2004 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents, maskwork
// rights, copyrights and other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design License
// Agreement (either as signed by you, agreed by you upon download or as a
// "click-through" agreement upon installation andor found at www.altera.com).
// By using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation. In the event that you do
// not agree with such terms and conditions, you may not use the reference design
// file and please promptly destroy any copies you have made.
//
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without limitation,
// warranties of merchantability, non-infringement, or fitness for a particular
// purpose, are specifically disclaimed. By making this reference design file
// available, Altera expressly does not recommend, suggest or require that this
// reference design file be used in combination with any other product not
// provided by Altera.
// ================================================================================
module blender (
pixel_clk,
layer_1,
layer_0,
alpha,
result
);
input pixel_clk;
input [5:0] layer_1;
input [5:0] layer_0;
input [5:0] alpha;
output [5:0] result;
wire [5:0] one_minus_alpha_l_1;
wire [11:0] mult_out1;
wire [11:0] mult_out2;
wire [5:0] result;
//Create (1 - Alpha_layer_1)
adder_6bit_cin one_minus_alpha_1 (
.dataa (6'h3f),
.datab (~alpha),
.cin (1'b1),
.result (one_minus_alpha_l_1)
);
//multipliers
mult_6bit_clk mult_1 (
.clock (pixel_clk),
.dataa (layer_1),
.datab (alpha),
.result (mult_out1)
);
mult_6bit_clk mult_2 (
.clock (pixel_clk),
.dataa (layer_0),
.datab (one_minus_alpha_l_1),
.result (mult_out2)
);
//adder
adder_6bit add_1 (
.dataa (mult_out1[11:6]),
.datab (mult_out2[11:6]),
.result (result)
);
endmodule
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