lcd_controller.v

Altera的基于NIOS II的LCD控制器源代码

// ================================================================================
// (c) 2004 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents, maskwork
// rights, copyrights and other intellectual property laws.
// 
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design License
// Agreement (either as signed by you, agreed by you upon download or as a
// "click-through" agreement upon installation andor found at www.altera.com).
// By using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation.  In the event that you do
// not agree with such terms and conditions, you may not use the reference design
// file and please promptly destroy any copies you have made.
// 
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without limitation,
// warranties of merchantability, non-infringement, or fitness for a particular
// purpose, are specifically disclaimed.  By making this reference design file
// available, Altera expressly does not recommend, suggest or require that this
// reference design file be used in combination with any other product not
// provided by Altera.
// ================================================================================


module lcd_controller (
   reset_n,
   pixel_clk, //Pixel clock
   clk_av,  //Avalon clock
//Avalon Slave Interface
   s_address,
   s_chipselect,
   s_read_n,
   s_write_n,
   s_writedata,
   s_waitrequest,
   s_readdata,
   int,
//Avalon Master Interfaces
//Master #0
   m0_address,
   m0_read_n,
   m0_readdata,
   m0_waitrequest,
   m0_readdatavalid,
//Master #1
   m1_address,
   m1_read_n,
   m1_readdata,
   m1_waitrequest,
   m1_readdatavalid,
//Master #2
   m2_address,
   m2_read_n,
   m2_readdata,
   m2_waitrequest,
   m2_readdatavalid,
//Master #3
   m3_address,
   m3_read_n,
   m3_readdata,
   m3_waitrequest,
   m3_readdatavalid,
//Master #4
   m4_address,
   m4_read_n,
   m4_readdata,
   m4_waitrequest,
   m4_readdatavalid,
//To Lancelot board
   hsync,
   vsync,
   sync,
   blank,
   red,
   green,
   blue,
   m1,
   m2,
   sync_t
);

  // defaults
  parameter DEVICE = "Cyclone";  


input reset_n;
input pixel_clk;
input clk_av;

// Avalon DMA register slave
input [5:0] s_address;
input s_chipselect;
input s_read_n;
input s_write_n;
input [31:0] s_writedata;
output s_waitrequest;
output [31:0] s_readdata;
output int;

// Avalon DMA master0
output [31:0] m0_address;
output m0_read_n;
input [31:0] m0_readdata;
input m0_waitrequest;
input m0_readdatavalid;

// Avalon DMA master1
output [31:0] m1_address;
output m1_read_n;
input [31:0] m1_readdata;
input m1_waitrequest;
input m1_readdatavalid;

// Avalon DMA master2
output [31:0] m2_address;
output m2_read_n;
input [31:0] m2_readdata;
input m2_waitrequest;
input m2_readdatavalid;

// Avalon DMA master3
output [31:0] m3_address;
output m3_read_n;
input [31:0] m3_readdata;
input m3_waitrequest;
input m3_readdatavalid;

// Avalon DMA master4
output [31:0] m4_address;
output m4_read_n;
input [31:0] m4_readdata;
input m4_waitrequest;
input m4_readdatavalid;

//To Lancelot board
output hsync;
output vsync;
output sync;
output blank;
output [7:0] red;
output [7:0] green;
output [7:0] blue;
output m1;
output m2;
output sync_t;

wire  [5:0] r_in;
wire  [5:0] g_in;
wire  [5:0] b_in;
wire  m1;
wire  m2;
wire  sync_t;
wire  read_next_pixel;
wire  end_of_picture;

wire  hsync_int;
wire  vsync_int;
wire  sync_int;
wire  blank_int;
wire  [5:0] red_int;
wire  [5:0] green_int;
wire  [5:0] blue_int;
wire act_l0;
wire act_l1;
wire act_l2;
wire act_l3;
wire act_l4;
wire [17:0] lcd_data;
//from avalon masters
wire [17:0] pixel_lay0;
wire [17:0] pixel_lay1;
wire [17:0] pixel_lay2;
wire [17:0] pixel_lay3;
wire [17:0] pixel_lay4;
wire [5:0] alpha_lay1;
wire [5:0] alpha_lay2;
wire [5:0] alpha_lay3;
wire [5:0] alpha_lay4;
//from avalon slave interface
wire [5:0] const_alpha_lay1;
wire [5:0] const_alpha_lay2;
wire [5:0] const_alpha_lay3;
wire [5:0] const_alpha_lay4;
wire [15:0] background;
wire layer_0_on;
wire layer_1_on;
wire layer_2_on;
wire layer_3_on;
wire layer_4_on;
wire [11:0] win_l1_h_start;
wire [11:0] win_l1_h_stop;
wire [11:0] win_l1_v_start;
wire [11:0] win_l1_v_stop;
wire [11:0] win_l2_h_start;
wire [11:0] win_l2_h_stop;
wire [11:0] win_l2_v_start;
wire [11:0] win_l2_v_stop;
wire [11:0] win_l3_h_start;
wire [11:0] win_l3_h_stop;
wire [11:0] win_l3_v_start;
wire [11:0] win_l3_v_stop;
wire [11:0] win_l4_h_start;
wire [11:0] win_l4_h_stop;
wire [11:0] win_l4_v_start;
wire [11:0] win_l4_v_stop;
wire [31:0] layer_0_dma_start_addr;
wire [31:0] layer_0_dma_length;
wire [31:0] layer_1_dma_start_addr;
wire [31:0] layer_1_dma_length;
wire [31:0] layer_2_dma_start_addr;
wire [31:0] layer_2_dma_length;
wire [31:0] layer_3_dma_start_addr;
wire [31:0] layer_3_dma_length;
wire [31:0] layer_4_dma_start_addr;
wire [31:0] layer_4_dma_length;
wire dma_layer_0_on;
wire dma_layer_1_on;
wire dma_layer_2_on;
wire dma_layer_3_on;
wire dma_layer_4_on;
wire vblank;
wire int;


reg  hsync;
reg  vsync;
reg  sync;
reg  blank;
reg  [7:0] red;
reg  [7:0] green;
reg  [7:0] blue;

//Instantiate Avalon Slave Interface
avalon_slave_if avalon_slave_if (
  .reset_n (reset_n),
  .pixel_clk (pixel_clk),
  .clk_av (clk_av),  //Avalon clock
//Avalon Slave Interface
  .s_address (s_address),
  .s_chipselect (s_chipselect),
  .s_read_n (s_read_n),
  .s_write_n (s_write_n),
  .s_writedata (s_writedata),
  .s_waitrequest (s_waitrequest),
  .s_readdata (s_readdata),
  .int (int),
//Outputs to rest of LCD Controller
  .const_alpha_lay1 (const_alpha_lay1),
  .const_alpha_lay2 (const_alpha_lay2),
  .const_alpha_lay3 (const_alpha_lay3),
  .const_alpha_lay4 (const_alpha_lay4),
  .background (background),
  .layer_0_on (layer_0_on),
  .layer_1_on (layer_1_on),
  .layer_2_on (layer_2_on),
  .layer_3_on (layer_3_on),
  .layer_4_on (layer_4_on),
  .win_l1_h_start (win_l1_h_start),
  .win_l1_h_stop (win_l1_h_stop),
  .win_l1_v_start (win_l1_v_start),
  .win_l1_v_stop (win_l1_v_stop),
  .win_l2_h_start (win_l2_h_start),
  .win_l2_h_stop (win_l2_h_stop),
  .win_l2_v_start (win_l2_v_start),
  .win_l2_v_stop (win_l2_v_stop),
  .win_l3_h_start (win_l3_h_start),
  .win_l3_h_stop (win_l3_h_stop),
  .win_l3_v_start (win_l3_v_start),
  .win_l3_v_stop (win_l3_v_stop),
  .win_l4_h_start (win_l4_h_start),
  .win_l4_h_stop (win_l4_h_stop),
  .win_l4_v_start (win_l4_v_start),
  .win_l4_v_stop (win_l4_v_stop),
  .layer_0_dma_start_addr (layer_0_dma_start_addr),
  .layer_0_dma_length (layer_0_dma_length),
  .layer_1_dma_start_addr (layer_1_dma_start_addr),
  .layer_1_dma_length (layer_1_dma_length),
  .layer_2_dma_start_addr (layer_2_dma_start_addr),
  .layer_2_dma_length (layer_2_dma_length),
  .layer_3_dma_start_addr (layer_3_dma_start_addr),
  .layer_3_dma_length (layer_3_dma_length),
  .layer_4_dma_start_addr (layer_4_dma_start_addr),
  .layer_4_dma_length (layer_4_dma_length),
  .dma_layer_0_on (dma_layer_0_on),
  .dma_layer_1_on (dma_layer_1_on),
  .dma_layer_2_on (dma_layer_2_on),
  .dma_layer_3_on (dma_layer_3_on),
  .dma_layer_4_on (dma_layer_4_on),
  .vblank (vblank),
  .end_of_picture (end_of_picture)
);

//Avalon Master Interfaces
//Layer0
wire [15:0] rdata_layer0;

avalon_rd_dma_fifo  #(DEVICE, 7, 7, 32, 16, 128, 256, 6, 1) avalon_master_l0
  (
   .clk_f (pixel_clk),
   .clk_av (clk_av),
   .reset_n (reset_n),

   // FIFO read interface
   .rd (act_l0),
   .rdata (rdata_layer0),
   .empty (),

   // Avalon DMA master
   .m_address (m0_address),
   .m_read_n (m0_read_n),
   .m_readdata (m0_readdata),
   .m_waitrequest (m0_waitrequest),
   .m_readdatavalid (m0_readdatavalid),

   // Register interface
   .dma_start_addr (layer_0_dma_start_addr),
   .dma_length (layer_0_dma_length),
   .dma_layer_on (dma_layer_0_on)
   );

//Layer1
wire [15:0] rdata_layer1;

avalon_rd_dma_fifo #(DEVICE, 7, 7, 32, 16, 128, 256, 6, 1) avalon_master_l1
  (
   .clk_f (pixel_clk),
   .clk_av (clk_av),
   .reset_n (reset_n),

   // FIFO read interface
   .rd (act_l1),
   .rdata (rdata_layer1),
   .empty (),

   // Avalon DMA master
   .m_address (m1_address),
   .m_read_n (m1_read_n),
   .m_readdata (m1_readdata),
   .m_waitrequest (m1_waitrequest),
   .m_readdatavalid (m1_readdatavalid),

   // Register interface
   .dma_start_addr (layer_1_dma_start_addr),
   .dma_length (layer_1_dma_length),
   .dma_layer_on (dma_layer_1_on)
   );

//Layer2
wire [7:0] rdata_layer2;

avalon_rd_dma_fifo #(DEVICE, 7, 7, 32, 8, 128, 512, 6, 2) avalon_master_l2
  (
   .clk_f (pixel_clk),
   .clk_av (clk_av),
   .reset_n (reset_n),

   // FIFO read interface
   .rd (act_l2),
   .rdata (rdata_layer2),
   .empty (),

   // Avalon DMA master
   .m_address (m2_address),
   .m_read_n (m2_read_n),
   .m_readdata (m2_readdata),
   .m_waitrequest (m2_waitrequest),
   .m_readdatavalid (m2_readdatavalid),

   // Register interface
   .dma_start_addr (layer_2_dma_start_addr),
   .dma_length (layer_2_dma_length),
   .dma_layer_on (dma_layer_2_on)
   );

//Layer2 Palette
wire [23:0] rd_palette_l2;

sp_palette_rom l2_palette (
	.address (rdata_layer2),
	.clock (pixel_clk),
	.q (rd_palette_l2)
	);


//Layer3
wire [7:0] rdata_layer3;

avalon_rd_dma_fifo #(DEVICE, 7, 7, 32, 8, 128, 512, 6, 2) avalon_master_l3
  (
   .clk_f (pixel_clk),
   .clk_av (clk_av),
   .reset_n (reset_n),

   // FIFO read interface
   .rd (act_l3),
   .rdata (rdata_layer3),
   .empty (),

   // Avalon DMA master
   .m_address (m3_address),
   .m_read_n (m3_read_n),
   .m_readdata (m3_readdata),
   .m_waitrequest (m3_waitrequest),
   .m_readdatavalid (m3_readdatavalid),

   // Register interface
   .dma_start_addr (layer_3_dma_start_addr),
   .dma_length (layer_3_dma_length),
   .dma_layer_on (dma_layer_3_on)
   );

//Layer3 Palette
wire [23:0] rd_palette_l3;

sp_palette_rom l3_palette (
	.address (rdata_layer3),
	.clock (pixel_clk),
	.q (rd_palette_l3)
	);

//Layer4
wire [7:0] rdata_layer4;

avalon_rd_dma_fifo #(DEVICE, 7, 7, 32, 8, 128, 512, 6, 2) avalon_master_l4
  (
   .clk_f (pixel_clk),
   .clk_av (clk_av),
   .reset_n (reset_n),

   // FIFO read interface
   .rd (act_l4),
   .rdata (rdata_layer4),
   .empty (),

   // Avalon DMA master
   .m_address (m4_address),
   .m_read_n (m4_read_n),
   .m_readdata (m4_readdata),
   .m_waitrequest (m4_waitrequest),
   .m_readdatavalid (m4_readdatavalid),

   // Register interface
   .dma_start_addr (layer_4_dma_start_addr),
   .dma_length (layer_4_dma_length),
   .dma_layer_on (dma_layer_4_on)
   );

//Layer4 Palette
wire [23:0] rd_palette_l4;

sp_palette_rom l4_palette (
	.address (rdata_layer4),
	.clock (pixel_clk),
	.q (rd_palette_l4)
	);


assign pixel_lay0 = layer_0_on ? {rdata_layer0[15:11], 1'b1, rdata_layer0[10:5], rdata_layer0[4:0], 1'b1} : 18'h00000;
assign pixel_lay1 = layer_1_on ? {rdata_layer1[15:11], 1'b1, rdata_layer1[10:5], rdata_layer1[4:0], 1'b1} : 18'h00000;
assign pixel_lay2 = layer_2_on ? rd_palette_l2[17:0] : 18'h00000;
assign pixel_lay3 = layer_3_on ? rd_palette_l3[17:0] : 18'h00000;
assign pixel_lay4 = layer_4_on ? rd_palette_l4[17:0] : 18'h00000;

assign alpha_lay1 = layer_1_on ? (act_l1 ? 6'h3f : 6'h00) : 6'h00; //Video layer, no pixel_alpha
assign alpha_lay2 = layer_2_on ? (act_l2 ? rd_palette_l2[23:18] : 6'h00) : 6'h00;
assign alpha_lay3 = layer_3_on ? (act_l3 ? rd_palette_l3[23:18] : 6'h00) : 6'h00;
assign alpha_lay4 = layer_4_on ? (act_l4 ? rd_palette_l4[23:18] : 6'h00) : 6'h00;

//Instantiate Pixel Engine
//3 colours, 6-bit/pixel, 6-bit alpha/layer, 5-layers
pixel_engine pixel_engine (
//inputs
.pixel_clk (pixel_clk),
.rst_n (reset_n),
.pixel_lay0 (pixel_lay0),
.pixel_lay1 (pixel_lay1),
.alpha_lay1 (alpha_lay1),
.const_alpha_lay1 (const_alpha_lay1),
.pixel_lay2 (pixel_lay2),
.alpha_lay2 (alpha_lay2),
.const_alpha_lay2 (const_alpha_lay2),
.pixel_lay3 (pixel_lay3),
.alpha_lay3 (alpha_lay3),
.const_alpha_lay3 (const_alpha_lay3), 
.pixel_lay4 (pixel_lay4),
.alpha_lay4 (alpha_lay4),
.const_alpha_lay4 (const_alpha_lay4),
.background (background),
//control inputs
.layer_0_on (layer_0_on),
.layer_1_on (layer_1_on),
.layer_2_on (layer_2_on),
.layer_3_on (layer_3_on),
.layer_4_on (layer_4_on),
//outputs
.lcd_data (lcd_data)
);

assign b_in = lcd_data[5:0];
assign g_in = lcd_data[11:6];
assign r_in = lcd_data[17:12];


//Instantiate VGA Timing Generator
vga_timing vga_timing ( 
// inputs
	.vga_clk  (pixel_clk),
	.reset  (~reset_n),
	.R_in  (r_in),
	.G_in  (g_in),
	.B_in  (b_in),
	.win_l1_h_start (win_l1_h_start),
	.win_l1_h_stop (win_l1_h_stop),
	.win_l1_v_start (win_l1_v_start),
	.win_l1_v_stop (win_l1_v_stop),
	.win_l2_h_start (win_l2_h_start),
	.win_l2_h_stop (win_l2_h_stop),
	.win_l2_v_start (win_l2_v_start),
	.win_l2_v_stop (win_l2_v_stop),
	.win_l3_h_start (win_l3_h_start),
	.win_l3_h_stop (win_l3_h_stop),
	.win_l3_v_start (win_l3_v_start),
	.win_l3_v_stop (win_l3_v_stop),
	.win_l4_h_start (win_l4_h_start),
	.win_l4_h_stop (win_l4_h_stop),
	.win_l4_v_start (win_l4_v_start),
	.win_l4_v_stop (win_l4_v_stop),
//outputs
	.hsync  (hsync_int),
	.vsync  (vsync_int),
	.sync  (sync_int),
	.blank  (blank_int),
	.R  (red_int),
	.G  (green_int),
	.B  (blue_int),
	.read_next_pixel  (read_next_pixel),
	.end_of_picture  (end_of_picture),
	.act_l0 (act_l0),
	.act_l1 (act_l1),
	.act_l2 (act_l2),
	.act_l3 (act_l3),
	.act_l4 (act_l4),
	.vblank (vblank)
);

//Lancelot board DAC settings
assign m1 = 1'b0;
assign m2 = 1'b0;
assign sync_t = 1'b0;

//Output registers
always @(negedge pixel_clk or negedge reset_n)
begin
  if (~reset_n)
  begin
    hsync <= 'b0;
    vsync <= 'b0;
    sync <= 'b0;
    blank <= 'b0;
    red <= 'b0;
    green <= 'b0;
    blue <= 'b0;
  end
  else
  begin
    hsync <= hsync_int;
    vsync <= vsync_int;
    sync <= sync_int;
    blank <= blank_int;
    red <= {red_int, 2'b11}; //6-bit pixel_engine, 8-bit output DAC
    green <= {green_int, 2'b11}; //6-bit pixel_engine, 8-bit output DAC
    blue <= {blue_int, 2'b11}; //6-bit pixel_engine, 8-bit output DAC
  end
end

endmodule