📄 video.vhd
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------------------------------------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 2/9/2006
-- Copyright : 2006, XESS Corp
-- Tool Versions : WebPACK 6.3.03i
--
-- Description:
-- This is a simple design to grab frames of video data and display them on a VGA monitor.
-- When a button is pressed, the video codec dumps a stream of pixels in ITU-R BT.656 format,
-- 8-bit 4:2:2 with embedded syncs to the framegrabber module using a sampling clock of 27 MHz.
-- The framegrabber loads the pixels into a FIFO (along with some framing information).
-- A finite-state machine (FSM) offloads the pixels from the FIFO at 50 MHz and stores the
-- pixels into SDRAM while interleaving the lines of video from the odd and even fields.
-- Another address counter is used to read stored pixels from the SDRAM at 50 MHz and load them
-- into a FIFO. The VGA generator retrieves pixels from this FIFO and displays them on a monitor.
-- __________
-- | | _________ ______________
-- | Parallel | | | | | __________
-- | Port | | Button | | Address Cntr | | |
-- |__________| |_________| | + FSM |--->| |
-- | | |______________| | |
-- | | | |
-- ____V____ ____V____ ______________ | | ____________ _______
-- | | | | | | | | | | | |
-- | Video |--->| Frame |--->| FIFO |--->| | | | | |
-- | Codec | | Grabber | |______________| | | | | | |
-- |_________| |_________| | | | SDRAM | | |
-- | Dualport |<--->| Controller |<--->| SDRAM |
-- _________ _________ ______________ | | | | | |
-- | | | | | | | | | | | |
-- | Monitor |<---| VGA |<---| FIFO |<---| | | | | |
-- |_________| |_________| |______________| | | |____________| |_______|
-- | |
-- ______________ | |
-- | | | |
-- | Address Cntr |--->| |
-- |______________| |__________|
--
-- Revision:
-- 1.0.0
--
-- Additional Comments:
-- 1.0.0:
-- Initial release.
--
-- License:
-- This code can be freely distributed and modified as long as
-- this header is not removed.
------------------------------------------------------------------------------------------------
library ieee, unisim, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.framegrabber_pckg.all;
use unisim.vcomponents.all;
use work.vga_pckg.all;
use work.xsasdram.all;
use work.sdram.all;
use work.common.all;
entity video is
generic(
SDRAM_NROWS : natural := 8192; -- 4096 for XSA-50, XSA-100; 8192 for XSA-200, XSA-3S1000
SDRAM_NCOLS : natural := 512; -- 256 for XSA-50; 512 for XSA-100, XSA-200, XSA-3S1000
DATA_WIDTH : natural := 16; -- SDRAM databus width
SADDR_WIDTH : natural := 13; -- # of SDRAM address bits
HADDR_WIDTH : natural := 24; -- host-side address width
MASTER_CLK_FREQ : natural := 100_000; -- master clock frequency
MASTER_CLK_DIV : real := 2.0; -- SDRAM frequency = MASTER_CLK_FREQ / MASTER_CLK_DIV
VGA_CLK_FREQ : natural := 50_000; -- pixel clock = MASTER_CLK_FREQ / MASTER_CLK_DIV
PIXEL_WIDTH : natural := 16; -- width of a pixel in memory
NUM_RGB_BITS : natural := 3; -- #bits in each R,G,B component of a pixel
PIXELS_PER_LINE : natural := 720; -- width of image in pixels
LINES_PER_FRAME : natural := 525; -- height of image in scanlines
FIT_TO_SCREEN : boolean := false -- adapt video timing to fit image width x height
);
port(
clk_in : in std_logic; -- master clock (100 MHz)
grab_frame_n : in std_logic; -- active-low signal to initiate capture of a video frame
-- video decoder interface
vidin_clk : in std_logic; -- video decoder clock (27 MHz)
vidin_y : in std_logic_vector(7 downto 0); -- sampled video data
status : out std_logic_vector(7 downto 0); -- FSM status for debugging
-- VGA monitor interface
r : out std_logic_vector(NUM_RGB_BITS-1 downto 0); -- red
g : out std_logic_vector(NUM_RGB_BITS-1 downto 0); -- green
b : out std_logic_vector(NUM_RGB_BITS-1 downto 0); -- blue
hsync_n : out std_logic; -- horizontal sync
vsync_n : out std_logic; -- vertical sync
-- SDRAM interface
sclkfb : in std_logic; -- clock from SDRAM after PCB delays
sclk : out std_logic; -- SDRAM clock sync'ed to master clock
cke : out std_logic; -- clock-enable to SDRAM
cs_n : out std_logic; -- chip-select to SDRAM
ras_n : out std_logic; -- SDRAM row address strobe
cas_n : out std_logic; -- SDRAM column address strobe
we_n : out std_logic; -- SDRAM write enable
ba : out std_logic_vector(1 downto 0); -- SDRAM bank address bits
sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address
sData : inout std_logic_vector(DATA_WIDTH-1 downto 0); -- SDRAM in/out databus
dqmh : out std_logic; -- high databits I/O mask
dqml : out std_logic; -- low databits I/O mask
-- PC-to-video decoder I2C interface
lp_d : in std_logic_vector(1 downto 0); -- parallel port data pins
lp_s : out std_logic_vector(4 downto 3); -- parallel port status pins
scl : inout std_logic; -- bidirectional I2C clock signal
sda : inout std_logic -- bidirectional I2C data signal
);
end video;
architecture arch of video is
signal clk : std_logic; -- clock derived from master clock and sync'ed to SDRAM clock
signal reset : std_logic; -- internal reset
signal reset_cnt : natural range 0 to 7; -- counter for assertion of internal reset
signal grab_frame_sync : std_logic_vector(2 downto 1); -- sync grab initiation to master clock
-- framegrabber->SDRAM interface
signal buffered_vidin_clk : std_logic; -- buffered clock from video decoder
signal pixel_avail : std_logic; -- indicates the availability of a pixel from the framegrabber
signal pixel_rd : std_logic; -- initiates the read of a pixel from the framegrabber
signal pixel_from_framegrabber : std_logic_vector(15 downto 0); -- pixel from framegrabber
signal store_wr : std_logic; -- initiates store of pixel to SDRAM
signal store_wr_begun : std_logic; -- indicates pixel store operation has begun
signal pixel_cntr, pixel_cntr_x : natural range 0 to PIXELS_PER_LINE-1; -- counts pixels within a line of video
signal store_cntr, store_cntr_x : natural range 0 to (2**HADDR_WIDTH)-1; -- address at which to store pixel
signal store_address : std_logic_vector(HADDR_WIDTH-1 downto 0); -- address at which to store pixel
type svs is (wait_for_pixel, store_pixel); -- framegrabber->SDRAM FSM states
signal store_state, store_state_x : svs; -- state of framegrabber->SDRAM FSM
-- SDRAM->VGA interface
signal vga_eof : std_logic; -- indicates the end of a frame of VGA video
signal vga_full : std_logic; -- indicates the FIFO to the VGA generator is full
signal read_rd : std_logic; -- initiates a read of a pixel from SDRAM
signal read_rd_begun : std_logic; -- indicates the pixel read operation has begun
signal read_rd_done : std_logic; -- indicates the SDRAM has delivered the pixel
signal pixel_to_vga : std_logic_vector(15 downto 0); -- pixel from SDRAM to VGA generator
signal read_cntr : natural range 0 to (2**HADDR_WIDTH)-1; -- address from which to read pixel
signal read_address : std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from which to read pixel
-- SDRAM-controller side of SDRAM dualport
signal rst_i : std_logic;
signal rd_i : std_logic;
signal wr_i : std_logic;
signal earlyOpBegun_i : std_logic;
signal opBegun_i : std_logic;
signal rdPending_i : std_logic;
signal done_i : std_logic;
signal rdDone_i : std_logic;
signal hAddr_i : std_logic_vector(HADDR_WIDTH-1 downto 0);
signal hDIn_i : std_logic_vector(DATA_WIDTH-1 downto 0);
signal hDOut_i : std_logic_vector(DATA_WIDTH-1 downto 0);
signal status_i : std_logic_vector(3 downto 0);
-- I2C interface signals
signal scl_out : std_logic; -- output on I2C clock line
signal scl_in : std_logic; -- input from I2C clock line
signal sda_out : std_logic; -- output on I2C data line
signal sda_in : std_logic; -- input from I2C data line
begin
----------------------------------------------------------------------------------------------
-- Generate a reset and release it after a few clocks.
----------------------------------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if reset_cnt = 7 then
reset <= NO;
else
reset <= YES;
reset_cnt <= reset_cnt + 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------
-- Synchronize the framegrabber initiation input to the clock domain by passing it
-- through a chain of flip-flops.
----------------------------------------------------------------------------------------------
process(clk, reset)
begin
if reset = YES then
grab_frame_sync <= "00";
elsif rising_edge(clk) then
grab_frame_sync <= grab_frame_sync(grab_frame_sync'high-1 downto 1) & not grab_frame_n;
end if;
end process;
----------------------------------------------------------------------------------------------
-- The framegrabber module interfaces to the video codec and delivers the pixels.
----------------------------------------------------------------------------------------------
ux: ibuf port map(I=>vidin_clk,O=>buffered_vidin_clk); -- Buffer the clock input for the XSA-200.
u0 : framegrabber port map (
reset => reset,
video_clk => buffered_vidin_clk,
video_in => vidin_y,
grab_frame => grab_frame_sync(grab_frame_sync'high),
pixel_clk => clk,
pixel_avail => pixel_avail,
pixel_rd => pixel_rd,
pixel_out => pixel_from_framegrabber,
status => status
);
----------------------------------------------------------------------------------------------
-- This FSM controls the transfer of pixels from the framegrabber module into the SDRAM.
----------------------------------------------------------------------------------------------
-- Combinational portion of the FSM
process(store_cntr, pixel_cntr, store_state, pixel_avail, pixel_from_framegrabber, store_wr_begun)
begin
-- Set the default values for these signals.
pixel_rd <= NO;
store_wr <= NO;
store_cntr_x <= store_cntr;
pixel_cntr_x <= pixel_cntr;
store_state_x <= store_state;
case store_state is
when wait_for_pixel =>
if pixel_avail = YES then
-- A pixel is available from the framegrabber, so read it and store it into SDRAM.
pixel_rd <= YES;
store_state_x <= store_pixel;
end if;
when store_pixel =>
-- The upper two bits of the pixel indicate the current field of the interleaved
-- video (bit 14) and whether the field has just changed (bit 15 is the sync bit).
-- A pixel with the sync bit set does not contain any valid pixel data so it isn't stored
-- into SDRAM. It is just used to reset the counter to the appropriate address for
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