jpeg_decode.vhd

PictureBrowser 是基于Altera 的DE2 开发板设计图像浏览器

-------------------------------------------------------------------------------
--
-- JPEG_decode
--
-- Modified 5/05/2007
-- Ian Roth
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity JPEG_decode is
  
  port (
	avs_s6_clk,
	avs_s6_chipselect,
	avs_s6_reset_n,
	avs_s6_read,
	avs_s6_write : in std_logic;
	avs_s6_address: in std_logic_vector(3 downto 0);
	avs_s6_writedata : in signed(31 downto 0);
	avs_s6_readdata : out signed(31 downto 0)
  );

end JPEG_decode;

architecture rtl of JPEG_decode is

component reggate is

  port (
	clk,reset_n : in std_logic;
	input : in signed(31 downto 0);
	enable : in std_logic;
	output : out signed(31 downto 0)
  );

end component reggate;

component mux is

  port (
	input0, input1, input2, input3,
	input4, input5, input6, input7 : in signed(31 downto 0);
	sel : in std_logic_vector(2 downto 0);
	output : out signed(31 downto 0)
  );
end component mux;

component quantmux is

  port (
	input : in signed(31 downto 0);
	dequant : in signed(31 downto 0);
	output : out signed(31 downto 0)
  );

end component quantmux;

  constant cos0 : signed(31 downto 0) :=  "00000000000000000000100110001110";-- 2446 FIX(0.298631336)
  constant cos1 : signed(31 downto 0) :=  "00000000000000000000110001111100";-- 3196 FIX(0.390180644)
  constant cos2 : signed(31 downto 0) :=  "00000000000000000001000101010001";-- 4433 FIX(0.541196100)
  constant cos3 : signed(31 downto 0) :=  "00000000000000000001100001111110";-- 6270 FIX(0.765366865)
  constant cos4 : signed(31 downto 0) :=  "00000000000000000001110011001101";-- 7373 FIX(0.899976223)
  constant cos5 : signed(31 downto 0) :=  "00000000000000000010010110100001";-- 9633 FIX(1.175875602)
  constant cos6 : signed(31 downto 0) :=  "00000000000000000011000000001011";-- 12299 FIX(1.501321110)
  constant cos7 : signed(31 downto 0) :=  "00000000000000000011101100100001";-- 15137 FIX(1.847759065)
  constant cos8 : signed(31 downto 0) :=  "00000000000000000011111011000101";-- 16069 FIX(1.961570560)
  constant cos9 : signed(31 downto 0) :=  "00000000000000000100000110110011";-- 16819 FIX(2.053119869)
  constant cos10 : signed(31 downto 0):=  "00000000000000000101001000000011";-- 20995 FIX(2.562915447)
  constant cos11 : signed(31 downto 0):=  "00000000000000000110001001010100";-- 25172 FIX(3.072711026)
  constant ncos1 : signed(31 downto 0) :=  "11111111111111111111001110000100";-- 3196 FIX(0.390180644)
  constant ncos4 : signed(31 downto 0) :=  "11111111111111111110001100110011";-- 7373 FIX(0.899976223)
  constant ncos7 : signed(31 downto 0) :=  "11111111111111111100010011011111";-- 15137 FIX(1.847759065)
  constant ncos8 : signed(31 downto 0) :=  "11111111111111111100000100111011";-- 16069 FIX(1.961570560)
  constant ncos10 : signed(31 downto 0):=  "11111111111111111010110111111101";-- 20995 FIX(2.562915447)

  signal enable0,enable1,enable2,enable3,enable4,enable5,enable6,enable7,
		 enable8,enable9,enable10,enable11,enable12,enable13,enable14,enable15 : std_logic;
  signal tobus : signed(31 downto 0);
  signal enableout : std_logic;
  signal enable : std_logic_vector(15 downto 0);
  signal dequant0,
		 dequant1,
		 dequant2,
		 dequant3,
		 dequant4,
		 dequant5,
		 dequant6,
		 dequant7 : signed(31 downto 0);
  signal input0,
		 input1,
		 input2,
		 input3,
		 input4,
		 input5,
		 input6,
		 input7 : signed(31 downto 0);
  signal stage10,
		 stage11,
		 stage12,
		 stage13,
		 stage14,
		 stage15,
		 stage16,
		 stage17 : signed(31 downto 0);
  signal stage22, stage23 : signed(63 downto 0);
  signal stage20,
		 stage21,
		 stage24,
		 stage25,
		 stage26,
		 stage27,
		 stage28,
		 stage29,
		 stage210,
		 stage211,
		 stage212 : signed(31 downto 0);
  signal stage30,
		 stage31,
		 stage32,
		 stage33,
		 stage34,
		 stage35,
		 stage36,
		 stage37,
		 stage38,
		 stage39,
		 stage310,
		 stage311,
		 stage312 : signed(63 downto 0);
  signal stage40,
		 stage41,
		 stage42,
		 stage43,
		 stage44,
		 stage45,
		 stage46,
		 stage47 : signed(63 downto 0);
  signal temp0, temp1, temp2, temp3, temp4, temp5, temp8 : signed(63 downto 0);
  signal temp6, temp7 : signed(31 downto 0);
  signal output0,
		 output1,
		 output2,
		 output3,
		 output4,
		 output5,
		 output6,
		 output7 : signed(31 downto 0);
		
begin

  REGMUX : mux port map (
    input0 => output0,
    input1 => output1,
    input2 => output2,
    input3 => output3,
    input4 => output4,
    input5 => output5,
    input6 => output6,
    input7 => output7,
    sel => avs_s6_address(2 downto 0),
	output => tobus
  );

  R0 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable0,
	output => input0
  );

  R1 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable2,
	output => input1
  );

  R2 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable4,
	output => input2
  );

  R3 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable6,
	output => input3
  );

  R4 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable8,
	output => input4
  );

  R5 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable10,
	output => input5
  );

  R6 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable12,
	output => input6
  );

  R7 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable14,
	output => input7
  );

  Q0 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable1,
	output => dequant0
  );

  Q1 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable3,
	output => dequant1
  );

  Q2 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable5,
	output => dequant2
  );

  Q3 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable7,
	output => dequant3
  );

  Q4 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable9,
	output => dequant4
  );

  Q5 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable11,
	output => dequant5
  );

  Q6 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable13,
	output => dequant6
  );

  Q7 : reggate port map (
	clk => avs_s6_clk,
	reset_n => avs_s6_reset_n,
	input => avs_s6_writedata,
	enable => enable15,
	output => dequant7
  );

  DE0 : quantmux port map (
	input => input0,
	dequant => dequant0,
	output => stage10
  );

  DE1 : quantmux port map (
	input => input1,
	dequant => dequant1,
	output => stage11
  );

  DE2 : quantmux port map (
	input => input2,
	dequant => dequant2,
	output => stage12
  );

  DE3 : quantmux port map (
	input => input3,
	dequant => dequant3,
	output => stage13
  );

  DE4 : quantmux port map (
	input => input4,
	dequant => dequant4,
	output => stage14
  );

  DE5 : quantmux port map (
	input => input5,
	dequant => dequant5,
	output => stage15
  );

  DE6 : quantmux port map (
	input => input6,
	dequant => dequant6,
	output => stage16
  );

  DE7 : quantmux port map (
	input => input7,
	dequant => dequant7,
	output => stage17
  );

  temp6 <= stage10 + stage14;
  temp7 <= stage10 - stage14;
  stage20 <= temp6(31) & temp6(17 downto 0) & "0000000000000"; -- shift by CONST_BITS
  stage21 <= temp7(31) & temp7(17 downto 0) & "0000000000000"; -- shift by CONST_BITS
  temp8 <= (stage12 + stage16) * cos2;
  stage22 <= (stage16 * ncos7) + temp8;
  stage23 <= (stage12 * cos3) + temp8;
  stage24 <= stage17;
  stage25 <= stage15;
  stage26 <= stage13;
  stage27 <= stage11;
  stage28 <= stage24 + stage27;
  stage29 <= stage25 + stage26;
  stage210 <= stage26 + stage24;
  stage211 <= stage25 + stage27;
  stage212 <= stage210 + stage211;
  stage30 <= stage20 + stage23;
  stage31 <= stage21 + stage22;
  stage32 <= stage21 - stage22;
  stage33 <= stage20 - stage23;
  stage34 <= stage24 * cos0; 
  stage35 <= stage25 * cos9;
  stage36 <= stage26 * cos11;
  stage37 <= stage27 * cos6;
  stage38 <= stage28 * ncos4;
  stage39 <= stage29 * ncos10;
  stage310 <= stage210 * ncos8;
  stage311 <= stage211 * ncos1;
  stage312 <= stage212 * cos5;
  temp0 <= stage310 + stage312;
  temp1 <= stage311 + stage312;
  temp2 <= stage34 + stage38 + temp0;
  temp3 <= stage35 + stage39 + temp1;
  temp4 <= stage36 + stage39 + temp0;
  temp5 <= stage37 + stage38 + temp1;
  stage40 <= stage30 + temp5;
  stage41 <= stage31 + temp4;
  stage42 <= stage32 + temp3;
  stage43 <= stage33 + temp2;
  stage44 <= stage33 - temp2;
  stage45 <= stage32 - temp3;
  stage46 <= stage31 - temp4;
  stage47 <= stage30 - temp5;
  output0 <= stage40(63) & stage40(30 downto 0); -- Reduce bit count for multiplied lines and keep the sign bit
  output1 <= stage41(63) & stage41(30 downto 0);
  output2 <= stage42(63) & stage42(30 downto 0);
  output3 <= stage43(63) & stage43(30 downto 0);
  output4 <= stage44(63) & stage44(30 downto 0);
  output5 <= stage45(63) & stage45(30 downto 0);
  output6 <= stage46(63) & stage46(30 downto 0);
  output7 <= stage47(63) & stage47(30 downto 0);

  enable0 <= avs_s6_write and enable(0) and avs_s6_chipselect;
  enable1 <= avs_s6_write and enable(1) and avs_s6_chipselect;
  enable2 <= avs_s6_write and enable(2) and avs_s6_chipselect;
  enable3 <= avs_s6_write and enable(3) and avs_s6_chipselect;
  enable4 <= avs_s6_write and enable(4) and avs_s6_chipselect;
  enable5 <= avs_s6_write and enable(5) and avs_s6_chipselect;
  enable6 <= avs_s6_write and enable(6) and avs_s6_chipselect;
  enable7 <= avs_s6_write and enable(7) and avs_s6_chipselect;   
  enable8 <= avs_s6_write and enable(8) and avs_s6_chipselect;
  enable9 <= avs_s6_write and enable(9) and avs_s6_chipselect;
  enable10 <= avs_s6_write and enable(10) and avs_s6_chipselect;
  enable11 <= avs_s6_write and enable(11) and avs_s6_chipselect;
  enable12 <= avs_s6_write and enable(12) and avs_s6_chipselect;
  enable13 <= avs_s6_write and enable(13) and avs_s6_chipselect;
  enable14 <= avs_s6_write and enable(14) and avs_s6_chipselect;
  enable15 <= avs_s6_write and enable(15) and avs_s6_chipselect;

  with avs_s6_address select
    enable <=	"0000000000000001"	when "0000",
				"0000000000000010"	when "0001",
				"0000000000000100"	when "0010",
				"0000000000001000"	when "0011",
				"0000000000010000"	when "0100",
				"0000000000100000"	when "0101",
				"0000000001000000"	when "0110",
				"0000000010000000"	when "0111",
				"0000000100000000"	when "1000",
				"0000001000000000"	when "1001",
				"0000010000000000"	when "1010",
				"0000100000000000"	when "1011",
				"0001000000000000"	when "1100",
				"0010000000000000"	when "1101",
				"0100000000000000"	when "1110",
				"1000000000000000"	when "1111",
				"0000000000000000"	when others;

  enableout <= avs_s6_read and avs_s6_chipselect;
				
  with enableout select
    avs_s6_readdata <= tobus when '1',
					   "00000000000000000000000000000000" when others;

end architecture rtl;