mux.vhd

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-- Modified 3/17/2007
-- Ian Roth

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux is

  port (
	input0, input1, input2, input3,
	input4, input5, input6, input7 : in signed(31 downto 0);
	sel : in std_logic_vector(2 downto 0);
	output : out signed(31 downto 0)
  );
end mux;

architecture behavior of mux is
begin
  with sel select
	output(31 downto 0) <=  input0(31 downto 0) when "000",
			  				input1(31 downto 0) when "001",
			  				input2(31 downto 0) when "010",
			  				input3(31 downto 0) when "011",
			  				input4(31 downto 0) when "100",
			  				input5(31 downto 0) when "101",
			  				input6(31 downto 0) when "110",
			  				input7(31 downto 0) when others;
end behavior;