test_vga.ucf

an-103005-vgagen.zip是一个VGA显示控制器

# timing constraint primarily to make the SDRAM controller operate at 100 MHz
NET      "clk"     TNM_NET   =      "clk"; 
TIMESPEC "TS_clk"  =         PERIOD "clk"  20 ns HIGH 50 %; 

net      rst_n     loc=p93;  # active-low reset from SW2 pushbutton
net      clk       loc=p88;  # main clock

# parallel port interface
net ppd<0>    loc=p50;  
net ppd<1>    loc=p48;  
net ppd<2>    loc=p42;  
net ppd<3>    loc=p47;  
net ppd<4>    loc=p65;  
net ppd<5>    loc=p51;  
# net ppd<6> loc=p58;
# net ppd<7> loc=p43;
net pps<3>    loc=p40;  
net pps<4>    loc=p29;  
net pps<5>    loc=p28;  
net pps<6>    loc=p78;  

# VGA signals
net      vsync_n   loc=p26;  # vertical sync
net      hsync_n   loc=p23;  # horizontal sync
net      red<0>    loc=p12;  # red component
net      red<1>    loc=p13;  
net      green<0>  loc=p19;  # green component 
net      green<1>  loc=p20;  
net      blue<0>   loc=p21;  # blue component
net      blue<1>   loc=p22;  

# SDRAM signals
net      sclk      loc=p129; # output clock to SDRAM
net      sclkfb    loc=p91;  # feedback of SDRAM clock after PCB delays
net      cke       loc=p131; # SDRAM clock enable
net      cs_n      loc=p132; # SDRAM chip-select
net      ras_n     loc=p130; # SDRAM RAS#
net      cas_n     loc=p126; # SDRAM	CAS#
net      we_n      loc=p123; # SDRAM write-enable
net      dqmh      loc=p124; # SDRAM databus upper-byte enable
net      dqml      loc=p122; # SDRAM databus lower-byte enable
net      sData<0>  loc=p95;  # SDRAM databus
net      sData<1>  loc=p99;  
net      sData<2>  loc=p101; 
net      sData<3>  loc=p103; 
net      sData<4>  loc=p113; 
net      sData<5>  loc=p115; 
net      sData<6>  loc=p117; 
net      sData<7>  loc=p120; 
net      sData<8>  loc=p121; 
net      sData<9>  loc=p118; 
net      sData<10> loc=p116; 
net      sData<11> loc=p114; 
net      sData<12> loc=p112; 
net      sData<13> loc=p102; 
net      sData<14> loc=p100; 
net      sData<15> loc=p96;  
net      sAddr<0>  loc=p141; # SDRAM address bus
net      sAddr<1>  loc=p4;   
net      sAddr<2>  loc=p6;   
net      sAddr<3>  loc=p10;  
net      sAddr<4>  loc=p11;  
net      sAddr<5>  loc=p7;   
net      sAddr<6>  loc=p5;   
net      sAddr<7>  loc=p3;   
net      sAddr<8>  loc=p140; 
net      sAddr<9>  loc=p138; 
net      sAddr<10> loc=p139; 
net      sAddr<11> loc=p136; 
net      sAddr<12> loc=p133; 
net      ba<0>     loc=p134; # SDRAM bank address
net      ba<1>     loc=p137;