test_vga.npl

an-103005-vgagen.zip是一个VGA显示控制器

JDF G
// Created by Project Navigator ver 1.0
PROJECT test-vga
DESIGN test_vga
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s1000
DEVICETIME 1098331222
DEVPKG ft256
DEVPKGTIME 1095687458
DEVSPEED -4
DEVSPEEDTIME 1095687458
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE test_vga.vhd
SOURCE ..\..\XSA_LIB\common.vhd
SOURCE ..\..\XSA_LIB\vga.vhd
SOURCE ..\..\XSA_LIB\xsasdramcntl.vhd
SOURCE ..\..\XSA_LIB\sdramcntl.vhd
SOURCE ..\..\XSA_LIB\xsasdramcntl_ppintfc.vhd
SOURCE ..\..\XSA_LIB\ramintfc_core.vhd
DEPASSOC test_vga test_vga.ucf
[Normal]
xilxBitgCfg_Clk=xstvhd, spartan3, Implementation.t_bitFile, 1098328394, Float
xilxBitgCfg_Done=xstvhd, spartan3, Implementation.t_bitFile, 1098328394, Float
xilxBitgCfg_M0=xstvhd, spartan3, Implementation.t_bitFile, 1098328394, Float
xilxBitgCfg_M1=xstvhd, spartan3, Implementation.t_bitFile, 1098328394, Float
xilxBitgCfg_M2=xstvhd, spartan3, Implementation.t_bitFile, 1098328394, Float
xilxBitgCfg_Pgm=xstvhd, spartan3, Implementation.t_bitFile, 1098328394, Float
xilxBitgCfg_TCK=xstvhd, spartan3, Implementation.t_bitFile, 1098328394, Float
xilxBitgCfg_TDI=xstvhd, spartan3, Implementation.t_bitFile, 1098328394, Float
xilxBitgCfg_TDO=xstvhd, spartan3, Implementation.t_bitFile, 1098328394, Float
xilxBitgCfg_TMS=xstvhd, spartan3, Implementation.t_bitFile, 1098328394, Float
xilxBitgCfg_Unused=xstvhd, spartan3, Implementation.t_bitFile, 1095910207, Float
[STATUS-ALL]
test_vga.ncdFile=WARNINGS,1201812099
test_vga.ngcFile=WARNINGS,1201812076
[STRATEGY-LIST]
Normal=True