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<title>VGA GENERATOR TEST APPLICATION WITH AN EMBEDDED PARALLEL PORT INTERFACE</title>
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<li><a href="#vga_generator_test_application_with_an_embedded_parallel_port_interface">VGA GENERATOR TEST APPLICATION WITH AN EMBEDDED PARALLEL PORT INTERFACE</a></li>
<li><a href="#source_files">SOURCE FILES</a></li>
<li><a href="#compiling_and_running_the_vga_generator_test_application">COMPILING AND RUNNING THE VGA GENERATOR TEST APPLICATION</a></li>
<li><a href="#embedding_a_parallel_port_interface_in_other_applications">EMBEDDING A PARALLEL PORT INTERFACE IN OTHER APPLICATIONS</a></li>
<li><a href="#see_also">SEE ALSO</a></li>
<li><a href="#author">AUTHOR</a></li>
<li><a href="#copyright_and_license">COPYRIGHT AND LICENSE</a></li>
<li><a href="#history">HISTORY</a></li>
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<h1><a name="vga_generator_test_application_with_an_embedded_parallel_port_interface">VGA GENERATOR TEST APPLICATION WITH AN EMBEDDED PARALLEL PORT INTERFACE</a></h1>
<p>This is a modification of the application originally described in
<a href="http://www.xess.com/appnotes/an-101204-vgagen.pdf">http://www.xess.com/appnotes/an-101204-vgagen.pdf</a> .
The original application was a combination of a VGA generator with an SDRAM controller
that could display an image stored in SDRAM on a VGA monitor.
The image had to be pre-loaded into the SDRAM on the XSA Board before the VGA generator was activated.</p>
<p>The current design removes that restriction and allows you to upload and download
images while the VGA generator is active.
This is achieved by combining the SDRAM controller with the dualport interface described in
<a href="http://www.xess.com/appnotes/an-071205-dualport.pdf">http://www.xess.com/appnotes/an-071205-dualport.pdf</a> .
A parallel port interface is attached to one of the ports and the VGA
generator is attached to the other.
Images can be transferred through the parallel port of a PC to the SDRAM
without disturbing the VGA generator as it accesses the SDRAM.</p>
<p>
</p>
<hr />
<h1><a name="source_files">SOURCE FILES</a></h1>
<dl>
<dt><strong><a name="item_xsa_lib_2fvga_2evhd_3a">XSA_LIB/vga.vhd:</a></strong>
<dd>
<p>This file describes the VGA generator circuit.</p>
</dd>
</li>
<dt><strong><a name="item_xsa_lib_2fsdramcntl_2evhd_3a">XSA_LIB/sdramcntl.vhd:</a></strong>
<dd>
<p>This file describes the core state machine of the SDRAM controller and the dualport module that
attaches to it to provide dual independent channels to/from the SDRAM.
See application note <a href="http://www.xess.com/appnotes/an-071205-dualport.pdf">http://www.xess.com/appnotes/an-071205-dualport.pdf</a> for details.</p>
</dd>
</li>
<dt><strong><a name="item_xsa_lib_2fxsasdramcntl_2evhd_3a">XSA_LIB/xsasdramcntl.vhd:</a></strong>
<dd>
<p>This file creates a wrapper around the SDRAM controller core to customize it for
the XSA Board.
See application note <a href="http://www.xess.com/appnotes/an-071205-xsasdramcntl.pdf">http://www.xess.com/appnotes/an-071205-xsasdramcntl.pdf</a> for details.</p>
</dd>
</li>
<dt><strong><a name="item_xsa_lib_2framintfc_core_2evhd_3a">XSA_LIB/ramintfc_core.vhd:</a></strong>
<dd>
<p>This file describes an interface that allows SDRAM address and data to be sent over the parallel port.</p>
</dd>
</li>
<dt><strong><a name="item_xsa_lib_2fxsasdramcntl_ppintfc_2evhd_3a">XSA_LIB/xsasdramcntl_ppintfc.vhd:</a></strong>
<dd>
<p>This file combines the XSA SDRAM controller, the dualport interface, and the parallel port interface.
The resulting module has a single SDRAM interface that is identical to that of the <em>xsasdramcntl.vhd</em> module,
and an additional port that connects to a few pins of the parallel port to provide access to the SDRAM from
an attached PC.</p>
</dd>
</li>
<dt><strong><a name="item_xsa_lib_2fcommon_2evhd_3a">XSA_LIB/common.vhd:</a></strong>
<dd>
<p>Some functions and definitions useful in many applications are provided in this file.</p>
</dd>
</li>
<dt><strong><a name="item__5b50_2c100_2c200_2c3s1000_5d_2ftest_vga_2ftest_vg">[50,100,200,3S1000]/test_vga/test_vga.vhd:</a></strong>
<dd>
<p>This is the top-level file that combines the SDRAM controller and the VGA generator
to create the complete test application for the XSA-50, XSA-100, XSA-200
or XSA-3S1000 Board.</p>
</dd>
</li>
<dt><strong>[50,100,200,3S1000]/test_vga/test_vga.ucf:</strong>
<dd>
<p>These are the pin assignments for mapping the VGA generator test application to
the XSA-50, XSA-100, XSA-200 or XSA-3S1000 Board.
These files also show the correct attachment of the pins from the parallel port to the FPGA in
order to upload/download the SDRAM using the GXSLOAD program.</p>
</dd>
</li>
<dt><strong>[50,100,200,3S1000]/test_vga/test_vga.npl:</strong>
<dd>
<p>This project file tells WebPACK how to combine the source files to create the
VGA generator test application for the XSA-50, XSA-100, XSA-200 or XSA-3S1000 Board.</p>
</dd>
</li>
<dt><strong>[50,100,200,3S1000]/test_vga/test_vga.bit:</strong>
<dd>
<p>This is a configuration bitstream that has already been generated for the XSA-50,
XSA-100, XSA-200 or XSA-3S1000 Board based on the files listed above.</p>
</dd>
</li>
<dt><strong><a name="item_image_2exes_3a">image.xes:</a></strong>
<dd>
<p>This is an image file that can be downloaded into the SDRAM on the XSA Board which
will then be displayed on a monitor by the VGA generator test application.</p>
</dd>
</li>
<dt><strong><a name="item_xsa_lib_2fvga_2dtiming_2exls_3a">XSA_LIB/vga-timing.xls:</a></strong>
<dd>
<p>This is a simple spreadsheet that calculates the durations of the various portions of
the horizontal and vertical sync signals given the height and width of the display and
the pixel clock frequency.</p>
</dd>
</li>
</dl>
<p>
</p>
<hr />
<h1><a name="compiling_and_running_the_vga_generator_test_application">COMPILING AND RUNNING THE VGA GENERATOR TEST APPLICATION</a></h1>
<ol>
<li>
<p>Open the project file for the VGA generator test application by double-clicking the
<em>test_vga.npl</em> file for your particular model of XSA Board.
All the compilation options can be set through the Project Navigator interface of WebPACK, and the generic
parameters that affect the operation of the VGA generator can be set in the test_vga.vhd file.
(The options for compiling a working application are already set in the files provided.)
Then double-click the ``Generate Programming File'' icon in the
Process pane and the bitstream will be generated.</p>
</li>
<li>
<p>The VGA generator test application needs a specific clock frequency to operate correctly.
For the XSA-50 and XSA-100 Boards, use GXSSETCLK to set the clock divisor to 2 so that a
50 MHz clock is available.
Nothing needs to be done for the XSA-200 or XSA-3S1000 Boards
since they have a fixed frequency 100 MHz oscillator.</p>
</li>
<li>
<p>Open the modified GXSLOAD downloading tool that was provided.
Drag-and-drop the <em>test_vga.bit</em> bitstream file generated
in step #1 into the FPGA pane of the GXSLOAD window.
Then click on the Load button to download this file to the FPGA on the XSA Board.</p>
</li>
<li>
<p>Connect a monitor to the VGA port of the XSA Board.
A random pattern of ``snow'' will appear on the monitor screen because the SDRAM has not
been initialized with image data, yet.</p>
</li>
<li>
<p>Double-click the <em>test_vga.bit</em> file in the GXSLOAD FPGA pane to de-select it.
Then drag-and-drop the <em>image.xes</em> file into the RAM pane.
Uncheck the ``Download RAM/Flash Interface'' box below the RAM pane to stop GXSLOAD
from overwriting the FPGA with the default SDRAM interface bitstream.
Then click on the Load button to download the image data to the SDRAM.</p>
</li>
<li>
<p>An image will appear on the monitor screen (beginning at the top of the screen and proceeding to the bottom)
as GXSLOAD downloads the contents of <em>image.xes</em> to the SDRAM.</p>
</li>
</ol>
<p>
</p>
<hr />
<h1><a name="embedding_a_parallel_port_interface_in_other_applications">EMBEDDING A PARALLEL PORT INTERFACE IN OTHER APPLICATIONS</a></h1>
<p>You can use the files in this application to provide access between the parallel port and the SDRAM in your own
application.
The necessary design files to include in your design are:
<em>sdramcntl.vhd</em>, <em>xsasdramcntl.vhd</em>, <em>ramintfc_core.vhd</em>, <em>xsasdramcntl_ppintfc.vhd</em>, and <em>common.vhd</em>.
You can also look in the <em>test_vga.ucf</em> file for your particular model of XSA Board to find the appropriate pin
assignments to the SDRAM and parallel port.
Then connect the logic for your application to the host-side interface shown in the <em>xsasdramcntl_ppintfc.vhd</em>
file in the same manner as you would the standard SDRAM controller in the <em>xsasdramcntl.vhd</em> file.
(Look at <a href="http://www.xess.com/appnotes/an-071205-xsasdramcntl.pdf">http://www.xess.com/appnotes/an-071205-xsasdramcntl.pdf</a> for details on how to use the
SDRAM controller.)</p>
<p>
</p>
<hr />
<h1><a name="see_also">SEE ALSO</a></h1>
<p>Use the <em>img2xes.pl</em> Perl script to convert your own graphic files into a format that works
with the VGA generator circuit.
The most-current version of <em>img2xes.pl</em> can be found at <a href="http://wwww.xess.com/ho07000.html">http://wwww.xess.com/ho07000.html</a> .</p>
<p>
</p>
<hr />
<h1><a name="author">AUTHOR</a></h1>
<p>Dave Vanden Bout, X Engineering Software Systems Corp.</p>
<p>Send bug reports to <a href="mailto:bugs@xess.com.">bugs@xess.com.</a></p>
<p>
</p>
<hr />
<h1><a name="copyright_and_license">COPYRIGHT AND LICENSE</a></h1>
<p>Copyright 2005 by X Engineering Software Systems Corporation.</p>
<p>This library is free software; you may redistribute it and/or modify
it as long as you do not remove the attributions to the author or his employer.</p>
<p>
</p>
<hr />
<h1><a name="history">HISTORY</a></h1>
<p>12/20/07 - Version 1.1 - Updated <em>ramintfc_core.vhd</em> to filter-out glitches on the downloading clock
passed through the parallel port.</p>
<p>10/30/05 - Version 1.0</p>
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