counter20.vhd

来自「交通灯VHDL设计」· VHDL 代码 · 共 49 行

--counter20
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter20 is
port(E20:in std_logic;
     clk: in std_logic;
     bcd10,bcd1:buffer std_logic_vector(3 downto 0);
     c20:out std_logic);
end counter20;
architecture rtl of counter20 is
signal co_1:std_logic;
   begin
  process(clk,E20)
  begin
       if E20='1' then
          bcd1<="0000";
       else
        if clk='1' and clk'event then
            if bcd1="0000" then
               bcd1<="1001";
            else
               bcd1<=bcd1-'1';
            end if;
          end if;
        end if;
   end process;
 process(clk,E20,bcd1)
 begin 
   if E20='1' then
      bcd10<="0000";
      co_1<='0';
   else
     if clk='1' and clk'event then
       if bcd1="0001" and bcd10="0000" then 
         co_1<='1';
      elsif bcd1="0000" and bcd10="0000" then
         bcd10<="0001";
         co_1<='0';
      elsif bcd1="0000" then 
         bcd10<=bcd10-'1';
         co_1<='0';
      end if;
    end if;
  end if;
end process;
c20<=co_1;
end rtl;