jtd.tan.qmsg

交通灯VHDL设计

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register bcd1\[0\]~reg0 register co_1 113.64 MHz 8.8 ns Internal " "Info: Clock \"clk\" has Internal fmax of 113.64 MHz between source register \"bcd1\[0\]~reg0\" and destination register \"co_1\" (period= 8.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.200 ns + Longest register register " "Info: + Longest register to register delay is 5.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bcd1\[0\]~reg0 1 REG LC3_A1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A1; Fanout = 7; REG Node = 'bcd1\[0\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "" { bcd1[0]~reg0 } "NODE_NAME" } "" } } { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns rtl~47 2 COMB LC2_A1 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC2_A1; Fanout = 1; COMB Node = 'rtl~47'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "2.900 ns" { bcd1[0]~reg0 rtl~47 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 5.200 ns co_1 3 REG LC6_A1 2 " "Info: 3: + IC(0.600 ns) + CELL(1.700 ns) = 5.200 ns; Loc. = LC6_A1; Fanout = 2; REG Node = 'co_1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "2.300 ns" { rtl~47 co_1 } "NODE_NAME" } "" } } { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 76.92 % ) " "Info: Total cell delay = 4.000 ns ( 76.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 23.08 % ) " "Info: Total interconnect delay = 1.200 ns ( 23.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "5.200 ns" { bcd1[0]~reg0 rtl~47 co_1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.200 ns" { bcd1[0]~reg0 rtl~47 co_1 } { 0.000ns 0.600ns 0.600ns } { 0.000ns 2.300ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 5 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "" { clk } "NODE_NAME" } "" } } { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns co_1 2 REG LC6_A1 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_A1; Fanout = 2; REG Node = 'co_1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "2.500 ns" { clk co_1 } "NODE_NAME" } "" } } { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "5.300 ns" { clk co_1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out co_1 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 5 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "" { clk } "NODE_NAME" } "" } } { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns bcd1\[0\]~reg0 2 REG LC3_A1 7 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_A1; Fanout = 7; REG Node = 'bcd1\[0\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "2.500 ns" { clk bcd1[0]~reg0 } "NODE_NAME" } "" } } { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "5.300 ns" { clk bcd1[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out bcd1[0]~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "5.300 ns" { clk co_1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out co_1 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "5.300 ns" { clk bcd1[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out bcd1[0]~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "5.200 ns" { bcd1[0]~reg0 rtl~47 co_1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.200 ns" { bcd1[0]~reg0 rtl~47 co_1 } { 0.000ns 0.600ns 0.600ns } { 0.000ns 2.300ns 1.700ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "5.300 ns" { clk co_1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out co_1 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "5.300 ns" { clk bcd1[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out bcd1[0]~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk bcd1\[3\] bcd1\[3\]~reg0 14.000 ns register " "Info: tco from clock \"clk\" to destination pin \"bcd1\[3\]\" through register \"bcd1\[3\]~reg0\" is 14.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_55 5 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "" { clk } "NODE_NAME" } "" } } { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns bcd1\[3\]~reg0 2 REG LC8_A1 6 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_A1; Fanout = 6; REG Node = 'bcd1\[3\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "2.500 ns" { clk bcd1[3]~reg0 } "NODE_NAME" } "" } } { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "5.300 ns" { clk bcd1[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out bcd1[3]~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.600 ns + Longest register pin " "Info: + Longest register to pin delay is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bcd1\[3\]~reg0 1 REG LC8_A1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A1; Fanout = 6; REG Node = 'bcd1\[3\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "" { bcd1[3]~reg0 } "NODE_NAME" } "" } } { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(5.100 ns) 7.600 ns bcd1\[3\] 2 PIN PIN_8 0 " "Info: 2: + IC(2.500 ns) + CELL(5.100 ns) = 7.600 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'bcd1\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "7.600 ns" { bcd1[3]~reg0 bcd1[3] } "NODE_NAME" } "" } } { "counter5.vhd" "" { Text "D:/eda/jtd/counter5.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 67.11 % ) " "Info: Total cell delay = 5.100 ns ( 67.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 32.89 % ) " "Info: Total interconnect delay = 2.500 ns ( 32.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "7.600 ns" { bcd1[3]~reg0 bcd1[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { bcd1[3]~reg0 bcd1[3] } { 0.000ns 2.500ns } { 0.000ns 5.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "5.300 ns" { clk bcd1[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out bcd1[3]~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jtd" "UNKNOWN" "V1" "D:/eda/jtd/db/jtd.quartus_db" { Floorplan "D:/eda/jtd/" "" "7.600 ns" { bcd1[3]~reg0 bcd1[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.600 ns" { bcd1[3]~reg0 bcd1[3] } { 0.000ns 2.500ns } { 0.000ns 5.100ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 10 13:28:50 2007 " "Info: Processing ended: Wed Jan 10 13:28:50 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}