identity.vhd

交通灯VHDL设计

library ieee;
use  ieee.std_logic_1164.all;
entity identity is
port(Q0:in std_logic;
     Q1:in std_logic;
     R1:out std_logic;
     Y1:out std_logic;
     G1:out std_logic;
     R2:out std_logic;
     Y2: out std_logic;
    G2:out std_logic);
end identity ;
architecture behav of identity is
begin
process(Q1,Q0)
begin
if(Q1='0' and Q0='0')then
                  R2<='1';
                Y2<='0';
                G2<='0';
                R1<='0';
                Y1<='0';
                G1<='1';
elsif(Q1='0' and Q0='1')then
                 R2<='1';
                Y2<='0';
                G2<='0';
                R1<='0';
                Y1<='1';
                G1<='0';
elsif(Q1='1' and Q0='1')then
                 R2<='0';
                 Y2<='0';
                G2<='1';
                R1<='1';
                Y1<='0';
                G1<='0';

elsif(Q1='1' and Q0='0')then
                 R2<='0';
                Y2<='1';
                G2<='0';
                R1<='1';
                Y1<='0';
                G1<='0';

end if;
end process;
end behav;