control.vhd

来自「交通灯VHDL设计」· VHDL 代码 · 共 75 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity control is
port(clk:in std_logic;
      C60: in std_logic;
      C20:in std_logic;
      C5: in std_logic;
      Q0: out std_logic;
       E60:out std_logic;
       E20: out std_logic;
       E5:out std_logic;
         Q1: out std_logic );
end control;
architecture behav of control is
type state_type is(a,b,c,d);
signal y_present,y_next: state_type;
begin
process(C60,C20,C5)
begin
if clk'event and clk='0' then
y_present<=y_next;

end if;
end process;
process(clk)
begin 
case y_present is
when a=>
if(C60='1' and C20='0' and C5='0')then
  y_next<=b;
else y_next<=a;
  end if;
E60<='0';
E20<='1';   
E5<='1';
Q1<='0';
Q0<='0';
when b=>
if(C5='1' and C20='0' and C60='0')then
  y_next<=c;
else y_next<=b;
  end if;
E60<='1';
E20<='1';   
E5<='0';
Q1<='0';
Q0<='1';

when c=>
if(C60='0' and C20='1' and C5='0')then
  y_next<=d;
else y_next<=c;
  end if;
E60<='1';
E20<='0';   
E5<='1';
Q1<='1';
Q0<='1';

when d=>
if(C60='0' and C20='0' and C5='1')then
  y_next<=a;
else y_next<=d;
  end if;
E60<='1';
E20<='1';   
E5<='0';
Q1<='1';
Q0<='0';
when others=>null;
end case;
end process;
end behav;