counter5.vhd

交通灯VHDL设计

--counter5
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter5 is
port(E5:in std_logic;
     clk: in std_logic;
     bcd10,bcd1:buffer std_logic_vector(3 downto 0);
     c5:out std_logic);
end counter5;
architecture rtl of counter5 is
signal co_1:std_logic;
   begin
  process(clk,E5)
  begin
       if E5='1' then
          bcd1<="0000";
          co_1<='0';
       else
        if clk='1' and clk'event then
            if bcd1="0001" then
               co_1<='1';
               bcd1<=bcd1-'1';
            elsif bcd1="0000" then
               bcd1<="0100";
               co_1<='0';
            else
               bcd1<=bcd1-'1';
            end if;
          end if;
        end if;
   end process;
bcd10<="0000";
c5<=co_1;
end rtl;