jtd.tan.rpt

交通灯VHDL设计

; N/A   ; 113.64 MHz ( period = 8.800 ns )               ; bcd1[0]~reg0 ; co_1         ; clk        ; clk      ; None                        ; None                      ; 5.200 ns                ;
; N/A   ; 113.64 MHz ( period = 8.800 ns )               ; bcd1[1]~reg0 ; co_1         ; clk        ; clk      ; None                        ; None                      ; 5.200 ns                ;
; N/A   ; 113.64 MHz ( period = 8.800 ns )               ; bcd1[2]~reg0 ; co_1         ; clk        ; clk      ; None                        ; None                      ; 5.200 ns                ;
; N/A   ; 120.48 MHz ( period = 8.300 ns )               ; bcd1[3]~reg0 ; co_1         ; clk        ; clk      ; None                        ; None                      ; 4.700 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; co_1         ; co_1         ; clk        ; clk      ; None                        ; None                      ; 2.300 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[0]~reg0 ; bcd1[3]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.300 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[1]~reg0 ; bcd1[3]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.300 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[2]~reg0 ; bcd1[3]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.300 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[0]~reg0 ; bcd1[2]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.300 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[1]~reg0 ; bcd1[2]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.300 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[0]~reg0 ; bcd1[1]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.300 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[2]~reg0 ; bcd1[1]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.300 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[3]~reg0 ; bcd1[1]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.300 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[0]~reg0 ; bcd1[0]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.300 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[2]~reg0 ; bcd1[0]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.300 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[3]~reg0 ; bcd1[0]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.300 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[3]~reg0 ; bcd1[3]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.800 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[2]~reg0 ; bcd1[2]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.800 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[1]~reg0 ; bcd1[1]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.800 ns                ;
; N/A   ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; bcd1[1]~reg0 ; bcd1[0]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.800 ns                ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 14.000 ns  ; bcd1[3]~reg0 ; bcd1[3] ; clk        ;
; N/A   ; None         ; 13.900 ns  ; co_1         ; c5      ; clk        ;
; N/A   ; None         ; 13.100 ns  ; bcd1[2]~reg0 ; bcd1[2] ; clk        ;
; N/A   ; None         ; 13.100 ns  ; bcd1[1]~reg0 ; bcd1[1] ; clk        ;
; N/A   ; None         ; 13.100 ns  ; bcd1[0]~reg0 ; bcd1[0] ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Jan 10 13:28:48 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jtd -c jtd
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 113.64 MHz between source register "bcd1[0]~reg0" and destination register "co_1" (period= 8.8 ns)
    Info: + Longest register to register delay is 5.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A1; Fanout = 7; REG Node = 'bcd1[0]~reg0'
        Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC2_A1; Fanout = 1; COMB Node = 'rtl~47'
        Info: 3: + IC(0.600 ns) + CELL(1.700 ns) = 5.200 ns; Loc. = LC6_A1; Fanout = 2; REG Node = 'co_1'
        Info: Total cell delay = 4.000 ns ( 76.92 % )
        Info: Total interconnect delay = 1.200 ns ( 23.08 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_A1; Fanout = 2; REG Node = 'co_1'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
        Info: - Longest clock path from clock "clk" to source register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_A1; Fanout = 7; REG Node = 'bcd1[0]~reg0'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 2.500 ns
Info: tco from clock "clk" to destination pin "bcd1[3]" through register "bcd1[3]~reg0" is 14.000 ns
    Info: + Longest clock path from clock "clk" to source register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_A1; Fanout = 6; REG Node = 'bcd1[3]~reg0'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 7.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A1; Fanout = 6; REG Node = 'bcd1[3]~reg0'
        Info: 2: + IC(2.500 ns) + CELL(5.100 ns) = 7.600 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'bcd1[3]'
        Info: Total cell delay = 5.100 ns ( 67.11 % )
        Info: Total interconnect delay = 2.500 ns ( 32.89 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jan 10 13:28:50 2007
    Info: Elapsed time: 00:00:02