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📄 init.c

📁 GPS导航定位程序
💻 C
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    CH[0]._CODE_PHASE = TR(CH01_CODE_PHASE);
    CH[0]._CODE_DCO_PHASE = TR(CH01_CODE_DCO_PHASE);
    CH[0]._I_PROMPT = TR(CH01_I_PROMPT);
    CH[0]._Q_PROMPT = TR(CH01_Q_PROMPT);
    CH[0]._I_TRACK = TR(CH01_I_TRACK);
    CH[0]._Q_TRACK = TR(CH01_Q_TRACK);
    CH[0]._CARRIER_CYCLE_COUNTER_HIGH = TR(CH01_CARRIER_CYCLE_COUNTER_HIGH);
    CH[0]._CARRIER_CYCLE_COUNTER_LOW = TR(CH01_CARRIER_CYCLE_COUNTER_LOW);
    CH[0]._CARRIER_DCO_PHASE = TR(CH01_CARRIER_DCO_PHASE);
    CH[0]._ACCUM_RESET = TR(CH01_ACCUM_RESET);
#endif

#if(MAXCHANNELS>=2)
    CH[1]._SATCNTL = TR(CH02_SATCNTL);
    CH[1]._CARRIER_DCO_INCR_HIGH = TR(CH02_CARRIER_DCO_INCR_HIGH);
    CH[1]._CARRIER_DCO_INCR_LOW = TR(CH02_CARRIER_DCO_INCR_LOW);
    CH[1]._CODE_DCO_INCR_HIGH = TR(CH02_CODE_DCO_INCR_HIGH);
    CH[1]._CODE_DCO_INCR_LOW = TR(CH02_CODE_DCO_INCR_LOW);
    CH[1]._EPOCH_LOAD = TR(CH02_EPOCH_LOAD);
    CH[1]._EPOCH_CHECK = TR(CH02_EPOCH_CHECK);
    CH[1]._EPOCH_COUNT = TR(CH02_EPOCH_COUNT);
    CH[1]._CODE_PHASE = TR(CH02_CODE_PHASE);
    CH[1]._CODE_DCO_PHASE = TR(CH02_CODE_DCO_PHASE);
    CH[1]._I_PROMPT = TR(CH02_I_PROMPT);
    CH[1]._Q_PROMPT = TR(CH02_Q_PROMPT);
    CH[1]._I_TRACK = TR(CH02_I_TRACK);
    CH[1]._Q_TRACK = TR(CH02_Q_TRACK);
    CH[1]._CARRIER_CYCLE_COUNTER_HIGH = TR(CH02_CARRIER_CYCLE_COUNTER_HIGH);
    CH[1]._CARRIER_CYCLE_COUNTER_LOW = TR(CH02_CARRIER_CYCLE_COUNTER_LOW);
    CH[1]._CARRIER_DCO_PHASE = TR(CH02_CARRIER_DCO_PHASE);
    CH[1]._ACCUM_RESET = TR(CH02_ACCUM_RESET);
#endif

#if(MAXCHANNELS>=3)
    CH[2]._SATCNTL = TR(CH03_SATCNTL);
    CH[2]._CARRIER_DCO_INCR_HIGH = TR(CH03_CARRIER_DCO_INCR_HIGH);
    CH[2]._CARRIER_DCO_INCR_LOW = TR(CH03_CARRIER_DCO_INCR_LOW);
    CH[2]._CODE_DCO_INCR_HIGH = TR(CH03_CODE_DCO_INCR_HIGH);
    CH[2]._CODE_DCO_INCR_LOW = TR(CH03_CODE_DCO_INCR_LOW);
    CH[2]._EPOCH_LOAD = TR(CH03_EPOCH_LOAD);
    CH[2]._EPOCH_CHECK = TR(CH03_EPOCH_CHECK);
    CH[2]._EPOCH_COUNT = TR(CH03_EPOCH_COUNT);
    CH[2]._CODE_PHASE = TR(CH03_CODE_PHASE);
    CH[2]._CODE_DCO_PHASE = TR(CH03_CODE_DCO_PHASE);
    CH[2]._I_PROMPT = TR(CH03_I_PROMPT);
    CH[2]._Q_PROMPT = TR(CH03_Q_PROMPT);
    CH[2]._I_TRACK = TR(CH03_I_TRACK);
    CH[2]._Q_TRACK = TR(CH03_Q_TRACK);
    CH[2]._CARRIER_CYCLE_COUNTER_HIGH = TR(CH03_CARRIER_CYCLE_COUNTER_HIGH);
    CH[2]._CARRIER_CYCLE_COUNTER_LOW = TR(CH03_CARRIER_CYCLE_COUNTER_LOW);
    CH[2]._CARRIER_DCO_PHASE = TR(CH03_CARRIER_DCO_PHASE);
    CH[2]._ACCUM_RESET = TR(CH03_ACCUM_RESET);
#endif

#if(MAXCHANNELS>=4)
    CH[3]._SATCNTL = TR(CH04_SATCNTL);
    CH[3]._CARRIER_DCO_INCR_HIGH = TR(CH04_CARRIER_DCO_INCR_HIGH);
    CH[3]._CARRIER_DCO_INCR_LOW = TR(CH04_CARRIER_DCO_INCR_LOW);
    CH[3]._CODE_DCO_INCR_HIGH = TR(CH04_CODE_DCO_INCR_HIGH);
    CH[3]._CODE_DCO_INCR_LOW = TR(CH04_CODE_DCO_INCR_LOW);
    CH[3]._EPOCH_LOAD = TR(CH04_EPOCH_LOAD);
    CH[3]._EPOCH_CHECK = TR(CH04_EPOCH_CHECK);
    CH[3]._EPOCH_COUNT = TR(CH04_EPOCH_COUNT);
    CH[3]._CODE_PHASE = TR(CH04_CODE_PHASE);
    CH[3]._CODE_DCO_PHASE = TR(CH04_CODE_DCO_PHASE);
    CH[3]._I_PROMPT = TR(CH04_I_PROMPT);
    CH[3]._Q_PROMPT = TR(CH04_Q_PROMPT);
    CH[3]._I_TRACK = TR(CH04_I_TRACK);
    CH[3]._Q_TRACK = TR(CH04_Q_TRACK);
    CH[3]._CARRIER_CYCLE_COUNTER_HIGH = TR(CH04_CARRIER_CYCLE_COUNTER_HIGH);
    CH[3]._CARRIER_CYCLE_COUNTER_LOW = TR(CH04_CARRIER_CYCLE_COUNTER_LOW);
    CH[3]._CARRIER_DCO_PHASE = TR(CH04_CARRIER_DCO_PHASE);
    CH[3]._ACCUM_RESET = TR(CH04_ACCUM_RESET);
#endif

#if(MAXCHANNELS>=5)
    CH[4]._SATCNTL = TR(CH05_SATCNTL);
    CH[4]._CARRIER_DCO_INCR_HIGH = TR(CH05_CARRIER_DCO_INCR_HIGH);
    CH[4]._CARRIER_DCO_INCR_LOW = TR(CH05_CARRIER_DCO_INCR_LOW);
    CH[4]._CODE_DCO_INCR_HIGH = TR(CH05_CODE_DCO_INCR_HIGH);
    CH[4]._CODE_DCO_INCR_LOW = TR(CH05_CODE_DCO_INCR_LOW);
    CH[4]._EPOCH_LOAD = TR(CH05_EPOCH_LOAD);
    CH[4]._EPOCH_CHECK = TR(CH05_EPOCH_CHECK);
    CH[4]._EPOCH_COUNT = TR(CH05_EPOCH_COUNT);
    CH[4]._CODE_PHASE = TR(CH05_CODE_PHASE);
    CH[4]._CODE_DCO_PHASE = TR(CH05_CODE_DCO_PHASE);
    CH[4]._I_PROMPT = TR(CH05_I_PROMPT);
    CH[4]._Q_PROMPT = TR(CH05_Q_PROMPT);
    CH[4]._I_TRACK = TR(CH05_I_TRACK);
    CH[4]._Q_TRACK = TR(CH05_Q_TRACK);
    CH[4]._CARRIER_CYCLE_COUNTER_HIGH = TR(CH05_CARRIER_CYCLE_COUNTER_HIGH);
    CH[4]._CARRIER_CYCLE_COUNTER_LOW = TR(CH05_CARRIER_CYCLE_COUNTER_LOW);
    CH[4]._CARRIER_DCO_PHASE = TR(CH05_CARRIER_DCO_PHASE);
    CH[4]._ACCUM_RESET = TR(CH05_ACCUM_RESET);
#endif

#if(MAXCHANNELS>=6)
    CH[5]._SATCNTL = TR(CH06_SATCNTL);
    CH[5]._CARRIER_DCO_INCR_HIGH = TR(CH06_CARRIER_DCO_INCR_HIGH);
    CH[5]._CARRIER_DCO_INCR_LOW = TR(CH06_CARRIER_DCO_INCR_LOW);
    CH[5]._CODE_DCO_INCR_HIGH = TR(CH06_CODE_DCO_INCR_HIGH);
    CH[5]._CODE_DCO_INCR_LOW = TR(CH06_CODE_DCO_INCR_LOW);
    CH[5]._EPOCH_LOAD = TR(CH06_EPOCH_LOAD);
    CH[5]._EPOCH_CHECK = TR(CH06_EPOCH_CHECK);
    CH[5]._EPOCH_COUNT = TR(CH06_EPOCH_COUNT);
    CH[5]._CODE_PHASE = TR(CH06_CODE_PHASE);
    CH[5]._CODE_DCO_PHASE = TR(CH06_CODE_DCO_PHASE);
    CH[5]._I_PROMPT = TR(CH06_I_PROMPT);
    CH[5]._Q_PROMPT = TR(CH06_Q_PROMPT);
    CH[5]._I_TRACK = TR(CH06_I_TRACK);
    CH[5]._Q_TRACK = TR(CH06_Q_TRACK);
    CH[5]._CARRIER_CYCLE_COUNTER_HIGH = TR(CH06_CARRIER_CYCLE_COUNTER_HIGH);
    CH[5]._CARRIER_CYCLE_COUNTER_LOW = TR(CH06_CARRIER_CYCLE_COUNTER_LOW);
    CH[5]._CARRIER_DCO_PHASE = TR(CH06_CARRIER_DCO_PHASE);
    CH[5]._ACCUM_RESET = TR(CH06_ACCUM_RESET);
#endif

#if(MAXCHANNELS>=7)
    CH[6]._SATCNTL = TR(CH07_SATCNTL);
    CH[6]._CARRIER_DCO_INCR_HIGH = TR(CH07_CARRIER_DCO_INCR_HIGH);
    CH[6]._CARRIER_DCO_INCR_LOW = TR(CH07_CARRIER_DCO_INCR_LOW);
    CH[6]._CODE_DCO_INCR_HIGH = TR(CH07_CODE_DCO_INCR_HIGH);
    CH[6]._CODE_DCO_INCR_LOW = TR(CH07_CODE_DCO_INCR_LOW);
    CH[6]._EPOCH_LOAD = TR(CH07_EPOCH_LOAD);
    CH[6]._EPOCH_CHECK = TR(CH07_EPOCH_CHECK);
    CH[6]._EPOCH_COUNT = TR(CH07_EPOCH_COUNT);
    CH[6]._CODE_PHASE = TR(CH07_CODE_PHASE);
    CH[6]._CODE_DCO_PHASE = TR(CH07_CODE_DCO_PHASE);
    CH[6]._I_PROMPT = TR(CH07_I_PROMPT);
    CH[6]._Q_PROMPT = TR(CH07_Q_PROMPT);
    CH[6]._I_TRACK = TR(CH07_I_TRACK);
    CH[6]._Q_TRACK = TR(CH07_Q_TRACK);
    CH[6]._CARRIER_CYCLE_COUNTER_HIGH = TR(CH07_CARRIER_CYCLE_COUNTER_HIGH);
    CH[6]._CARRIER_CYCLE_COUNTER_LOW = TR(CH07_CARRIER_CYCLE_COUNTER_LOW);
    CH[6]._CARRIER_DCO_PHASE = TR(CH07_CARRIER_DCO_PHASE);
    CH[6]._ACCUM_RESET = TR(CH07_ACCUM_RESET);
#endif

#if(MAXCHANNELS>=8)
    CH[7]._SATCNTL = TR(CH08_SATCNTL);
    CH[7]._CARRIER_DCO_INCR_HIGH = TR(CH08_CARRIER_DCO_INCR_HIGH);
    CH[7]._CARRIER_DCO_INCR_LOW = TR(CH08_CARRIER_DCO_INCR_LOW);
    CH[7]._CODE_DCO_INCR_HIGH = TR(CH08_CODE_DCO_INCR_HIGH);
    CH[7]._CODE_DCO_INCR_LOW = TR(CH08_CODE_DCO_INCR_LOW);
    CH[7]._EPOCH_LOAD = TR(CH08_EPOCH_LOAD);
    CH[7]._EPOCH_CHECK = TR(CH08_EPOCH_CHECK);
    CH[7]._EPOCH_COUNT = TR(CH08_EPOCH_COUNT);
    CH[7]._CODE_PHASE = TR(CH08_CODE_PHASE);
    CH[7]._CODE_DCO_PHASE = TR(CH08_CODE_DCO_PHASE);
    CH[7]._I_PROMPT = TR(CH08_I_PROMPT);
    CH[7]._Q_PROMPT = TR(CH08_Q_PROMPT);
    CH[7]._I_TRACK = TR(CH08_I_TRACK);
    CH[7]._Q_TRACK = TR(CH08_Q_TRACK);
    CH[7]._CARRIER_CYCLE_COUNTER_HIGH = TR(CH08_CARRIER_CYCLE_COUNTER_HIGH);
    CH[7]._CARRIER_CYCLE_COUNTER_LOW = TR(CH08_CARRIER_CYCLE_COUNTER_LOW);
    CH[7]._CARRIER_DCO_PHASE = TR(CH08_CARRIER_DCO_PHASE);
    CH[7]._ACCUM_RESET = TR(CH08_ACCUM_RESET);
#endif

#if(MAXCHANNELS>=9)
    CH[8]._SATCNTL = TR(CH09_SATCNTL);
    CH[8]._CARRIER_DCO_INCR_HIGH = TR(CH09_CARRIER_DCO_INCR_HIGH);
    CH[8]._CARRIER_DCO_INCR_LOW = TR(CH09_CARRIER_DCO_INCR_LOW);
    CH[8]._CODE_DCO_INCR_HIGH = TR(CH09_CODE_DCO_INCR_HIGH);
    CH[8]._CODE_DCO_INCR_LOW = TR(CH09_CODE_DCO_INCR_LOW);
    CH[8]._EPOCH_LOAD = TR(CH09_EPOCH_LOAD);
    CH[8]._EPOCH_CHECK = TR(CH09_EPOCH_CHECK);
    CH[8]._EPOCH_COUNT = TR(CH09_EPOCH_COUNT);
    CH[8]._CODE_PHASE = TR(CH09_CODE_PHASE);
    CH[8]._CODE_DCO_PHASE = TR(CH09_CODE_DCO_PHASE);
    CH[8]._I_PROMPT = TR(CH09_I_PROMPT);
    CH[8]._Q_PROMPT = TR(CH09_Q_PROMPT);
    CH[8]._I_TRACK = TR(CH09_I_TRACK);
    CH[8]._Q_TRACK = TR(CH09_Q_TRACK);
    CH[8]._CARRIER_CYCLE_COUNTER_HIGH = TR(CH09_CARRIER_CYCLE_COUNTER_HIGH);
    CH[8]._CARRIER_CYCLE_COUNTER_LOW = TR(CH09_CARRIER_CYCLE_COUNTER_LOW);
    CH[8]._CARRIER_DCO_PHASE = TR(CH09_CARRIER_DCO_PHASE);
    CH[8]._ACCUM_RESET = TR(CH09_ACCUM_RESET);
#endif

#if(MAXCHANNELS>=10)
    CH[9]._SATCNTL = TR(CH10_SATCNTL);
    CH[9]._CARRIER_DCO_INCR_HIGH = TR(CH10_CARRIER_DCO_INCR_HIGH);
    CH[9]._CARRIER_DCO_INCR_LOW = TR(CH10_CARRIER_DCO_INCR_LOW);
    CH[9]._CODE_DCO_INCR_HIGH = TR(CH10_CODE_DCO_INCR_HIGH);
    CH[9]._CODE_DCO_INCR_LOW = TR(CH10_CODE_DCO_INCR_LOW);
    CH[9]._EPOCH_LOAD = TR(CH10_EPOCH_LOAD);
    CH[9]._EPOCH_CHECK = TR(CH10_EPOCH_CHECK);
    CH[9]._CODE_PHASE = TR(CH10_CODE_PHASE);
    CH[9]._EPOCH_COUNT = TR(CH10_EPOCH_COUNT);
    CH[9]._CODE_DCO_PHASE = TR(CH10_CODE_DCO_PHASE);
    CH[9]._I_PROMPT = TR(CH10_I_PROMPT);
    CH[9]._Q_PROMPT = TR(CH10_Q_PROMPT);
    CH[9]._I_TRACK = TR(CH10_I_TRACK);
    CH[9]._Q_TRACK = TR(CH10_Q_TRACK);
    CH[9]._CARRIER_CYCLE_COUNTER_HIGH = TR(CH10_CARRIER_CYCLE_COUNTER_HIGH);
    CH[9]._CARRIER_CYCLE_COUNTER_LOW = TR(CH10_CARRIER_CYCLE_COUNTER_LOW);
    CH[9]._CARRIER_DCO_PHASE = TR(CH10_CARRIER_DCO_PHASE);
    CH[9]._ACCUM_RESET = TR(CH10_ACCUM_RESET);
#endif

#if(MAXCHANNELS>=11)
    CH[10]._SATCNTL = TR(CH11_SATCNTL);
    CH[10]._CARRIER_DCO_INCR_HIGH = TR(CH11_CARRIER_DCO_INCR_HIGH);
    CH[10]._CARRIER_DCO_INCR_LOW = TR(CH11_CARRIER_DCO_INCR_LOW);
    CH[10]._CODE_DCO_INCR_HIGH = TR(CH11_CODE_DCO_INCR_HIGH);
    CH[10]._CODE_DCO_INCR_LOW = TR(CH11_CODE_DCO_INCR_LOW);
    CH[10]._EPOCH_LOAD = TR(CH11_EPOCH_LOAD);
    CH[10]._EPOCH_CHECK = TR(CH11_EPOCH_CHECK);
    CH[10]._CODE_PHASE = TR(CH11_CODE_PHASE);
    CH[10]._EPOCH_COUNT = TR(CH11_EPOCH_COUNT);
    CH[10]._CODE_DCO_PHASE = TR(CH11_CODE_DCO_PHASE);
    CH[10]._I_PROMPT = TR(CH11_I_PROMPT);
    CH[10]._Q_PROMPT = TR(CH11_Q_PROMPT);
    CH[10]._I_TRACK = TR(CH11_I_TRACK);
    CH[10]._Q_TRACK = TR(CH11_Q_TRACK);
    CH[10]._CARRIER_CYCLE_COUNTER_HIGH = TR(CH11_CARRIER_CYCLE_COUNTER_HIGH);
    CH[10]._CARRIER_CYCLE_COUNTER_LOW = TR(CH11_CARRIER_CYCLE_COUNTER_LOW);
    CH[10]._CARRIER_DCO_PHASE = TR(CH11_CARRIER_DCO_PHASE);
    CH[10]._ACCUM_RESET = TR(CH11_ACCUM_RESET);
#endif

#if(MAXCHANNELS>=12)
    CH[11]._SATCNTL = TR(CH12_SATCNTL);
    CH[11]._CARRIER_DCO_INCR_HIGH = TR(CH12_CARRIER_DCO_INCR_HIGH);
    CH[11]._CARRIER_DCO_INCR_LOW = TR(CH12_CARRIER_DCO_INCR_LOW);
    CH[11]._CODE_DCO_INCR_HIGH = TR(CH12_CODE_DCO_INCR_HIGH);
    CH[11]._CODE_DCO_INCR_LOW = TR(CH12_CODE_DCO_INCR_LOW);
    CH[11]._EPOCH_LOAD = TR(CH12_EPOCH_LOAD);
    CH[11]._EPOCH_CHECK = TR(CH12_EPOCH_CHECK);
    CH[11]._CODE_PHASE = TR(CH12_CODE_PHASE);
    CH[11]._EPOCH_COUNT = TR(CH12_EPOCH_COUNT);
    CH[11]._I_PROMPT = TR(CH12_I_PROMPT);
    CH[11]._CODE_DCO_PHASE = TR(CH12_CODE_DCO_PHASE);
    CH[11]._Q_PROMPT = TR(CH12_Q_PROMPT);
    CH[11]._I_TRACK = TR(CH12_I_TRACK);
    CH[11]._Q_TRACK = TR(CH12_Q_TRACK);
    CH[11]._CARRIER_CYCLE_COUNTER_HIGH = TR(CH12_CARRIER_CYCLE_COUNTER_HIGH);
    CH[11]._CARRIER_CYCLE_COUNTER_LOW = TR(CH12_CARRIER_CYCLE_COUNTER_LOW);
    CH[11]._CARRIER_DCO_PHASE = TR(CH12_CARRIER_DCO_PHASE);
    CH[11]._ACCUM_RESET = TR(CH12_ACCUM_RESET);
#endif

    for(channel=0;channel<MAXCHANNELS;channel++)
    {
	CH[channel].channel = channel;
	CH[channel].SV = IDLE;                   /* All channels are idle. */
	CH[channel].FrameSync = FALSE;
	CH[channel].FrameSyncAndTIC = FALSE;
	CH[channel].pCODEDCO = CH[channel].CODEDCO = CODE_DCO_ZERO_DOPPLER;
	CH[channel].pCARRDCO = CH[channel].CARRDCO = CARR_DCO_ZERO_DOPPLER;
    }

    /* Initialize the GP2021 chip in preparation for normal operation. */

    outpw(GPRESET,ASSERT_MASTER_RESET);            /* Assert master reset. */
    outpw(GPRESET,DEASSERT_MASTER_RESET);       /* De-assert master reset. */

    disable();
    outpw(TR(SYSTEM_CONFIG),WATCHDOG_OFF);         /* Switch off watchdog. */     
    outpw(TR(SYSTEM_SET_UP),ENABLE_INTERRUPTS);      /* Enable interrupts. */
    outpw(TR(RESET_CONTROL),ALL_CHANNELS);         /* Enable all channels. */
    enable();
}

/***************************************************************************
*
* Function: void HardwareTest(void)  
*
* Verifies that the GPS Builder interrupts, address bus and data bus are
* working.
*
* Input: None.
*
* Output: None.
*
* Return Value: None.
****************************************************************************/
void HardwareTest(void)
{
    int channel;                                  /* Channel loop counter. */

    unsigned cycle_count[MAXCHANNELS];             /* Carrier cycle count. */
    unsigned testdata;  /* Used to load the carrier cycle count registers. */

    unsigned long interrupt_count;        /* Number of interrupts counted. */

    InitialiseGP2021();                          /* Initialize the GP2021. */
    outpw(GPIMASK,UNMASK_INTERRUPT);                 /* Unmask interrupts. */

    /* Do the interrupt count test */

    printf("\n\nInterrupt Check.\n");

    GPIntCtr = 0;

    delay(101);                                         /* Wait for 101ms. */

    interrupt_count = GPIntCtr;

    if(interrupt_count<180 || interrupt_count>220)
    {
	outpw(GPIMASK,MASK_INTERRUPT);          /* Mask GP2021 interrupts. */
	printf("\n\nInterrupt count error.");
	printf("\n%lu interrupts were counted - there should have been" 
	       " 200.",interrupt_count);
	printf("\nCheck the values contained in GPSBLDR2.CFG with the board "

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