corraddr.h

GPS导航定位程序

/***************************************************************************
* Plessey GP2021-3 GPS Correlator register addresses (displacement from
* the device's base address). 17/02/95.
***************************************************************************/

/***************************************************************************
* Define the base address of each channel's control registers.
***************************************************************************/

#define CH01_CONTROL                     0x000
#define CH02_CONTROL                     0x020
#define CH03_CONTROL                     0x040
#define CH04_CONTROL                     0x060
#define CH05_CONTROL                     0x080
#define CH06_CONTROL                     0x0A0
#define CH07_CONTROL                     0x0C0
#define CH08_CONTROL                     0x0E0
#define CH09_CONTROL                     0x100
#define CH10_CONTROL                     0x120
#define CH11_CONTROL                     0x140
#define CH12_CONTROL                     0x160
#define MULTI_CONTROL                    0x180
#define ALL_CONTROL                      0x1C0

/***************************************************************************
* Define the base address of each channel's accumulate registers.
***************************************************************************/

#define CH01_ACCUMULATE                  0x210
#define CH02_ACCUMULATE                  0x220
#define CH03_ACCUMULATE                  0x230
#define CH04_ACCUMULATE                  0x240
#define CH05_ACCUMULATE                  0x250
#define CH06_ACCUMULATE                  0x260
#define CH07_ACCUMULATE                  0x270
#define CH08_ACCUMULATE                  0x280
#define CH09_ACCUMULATE                  0x290
#define CH10_ACCUMULATE                  0x2A0
#define CH11_ACCUMULATE                  0x2B0
#define CH12_ACCUMULATE                  0x2C0
#define MULTI_ACCUMULATE                 0x2D0
#define ALL_ACCUMULATE                   0x2E0

/***************************************************************************
* Define the offset from the base control address for each control
* register.
***************************************************************************/

/* First the read addresses */

#define CODE_SLEW_READ                   0x000
#define CODE_PHASE                       0x004
#define CARRIER_CYCLE_COUNTER_LOW        0x008
#define CARRIER_DCO_PHASE                0x00C
#define EPOCH_COUNT                      0x010
#define CODE_DCO_PHASE                   0x014
#define CARRIER_CYCLE_COUNTER_HIGH       0x018
#define EPOCH_CHECK                      0x01C

/* Now the write addresses */

#define SATCNTL                          0x000
#define CODE_PHASE_COUNTER               0x004
#define CARRIER_CYCLE_COUNTER            0x008
#define CARRIER_DCO_INCR_HIGH            0x00C
#define CARRIER_DCO_INCR_LOW             0x010
#define CODE_DCO_INCR_HIGH               0x014
#define CODE_DCO_INCR_LOW                0x018
#define EPOCH_LOAD                       0x01C

/***************************************************************************
* Define the offset from the base accumulate address for each accumulate
* register.
***************************************************************************/

/* First the read addresses */

#define I_TRACK                          0x000
#define Q_TRACK                          0x004
#define I_PROMPT                         0x008
#define Q_PROMPT                         0x00C

/* Now the write addresses */

#define CODE_SLEW_WRITE                  0x000
#define ACCUM_RESET                      0x004
#define CODE_DCO_PRESET_PHASE            0x00C

/***************************************************************************
* Define the address shift bewteen the correclator address lines and the
* PC address lines.
*
* The correlator addresses are all word aligned (2 LSBs zero) so that it
* possible to connect A<9:2> on the correlator to A<7:0> on the processor
* for non word aligned systems.
*
* Set ADDRESS_SHIFT as follows:
*
* Word aligned     : 0x000
*
* Non word aligned : 0x002
*
***************************************************************************/

#define ADDRESS_SHIFT                    0x002

/***************************************************************************
* Define each individual channel control register address as a function of
* the channel control register base address, the offset from the base and
* the address shift.
***************************************************************************/

/* Read */

#define CH01_CODE_SLEW_READ              ((CH01_CONTROL+CODE_SLEW_READ)>>ADDRESS_SHIFT)
#define CH01_CODE_PHASE                  ((CH01_CONTROL+CODE_PHASE)>>ADDRESS_SHIFT)
#define CH01_CARRIER_CYCLE_COUNTER_LOW   ((CH01_CONTROL+CARRIER_CYCLE_COUNTER_LOW)>>ADDRESS_SHIFT)
#define CH01_CARRIER_DCO_PHASE           ((CH01_CONTROL+CARRIER_DCO_PHASE)>>ADDRESS_SHIFT)
#define CH01_EPOCH_COUNT                 ((CH01_CONTROL+EPOCH_COUNT)>>ADDRESS_SHIFT)
#define CH01_CODE_DCO_PHASE              ((CH01_CONTROL+CODE_DCO_PHASE)>>ADDRESS_SHIFT)
#define CH01_CARRIER_CYCLE_COUNTER_HIGH  ((CH01_CONTROL+CARRIER_CYCLE_COUNTER_HIGH)>>ADDRESS_SHIFT)
#define CH01_EPOCH_CHECK                 ((CH01_CONTROL+EPOCH_CHECK)>>ADDRESS_SHIFT)

/* Write */

#define CH01_SATCNTL                     ((CH01_CONTROL+SATCNTL)>>ADDRESS_SHIFT)
#define CH01_CODE_PHASE_COUNTER          ((CH01_CONTROL+CODE_PHASE_COUNTER)>>ADDRESS_SHIFT)
#define CH01_CARRIER_CYCLE_COUNTER       ((CH01_CONTROL+CARRIER_CYCLE_COUNTER)>>ADDRESS_SHIFT)
#define CH01_CARRIER_DCO_INCR_HIGH       ((CH01_CONTROL+CARRIER_DCO_INCR_HIGH)>>ADDRESS_SHIFT)
#define CH01_CARRIER_DCO_INCR_LOW        ((CH01_CONTROL+CARRIER_DCO_INCR_LOW)>>ADDRESS_SHIFT)
#define CH01_CODE_DCO_INCR_HIGH          ((CH01_CONTROL+CODE_DCO_INCR_HIGH)>>ADDRESS_SHIFT)
#define CH01_CODE_DCO_INCR_LOW           ((CH01_CONTROL+CODE_DCO_INCR_LOW)>>ADDRESS_SHIFT)
#define CH01_EPOCH_LOAD                  ((CH01_CONTROL+EPOCH_LOAD)>>ADDRESS_SHIFT)

/* Read */

#define CH02_CODE_SLEW_READ              ((CH02_CONTROL+CODE_SLEW_READ)>>ADDRESS_SHIFT)
#define CH02_CODE_PHASE                  ((CH02_CONTROL+CODE_PHASE)>>ADDRESS_SHIFT)
#define CH02_CARRIER_CYCLE_COUNTER_LOW   ((CH02_CONTROL+CARRIER_CYCLE_COUNTER_LOW)>>ADDRESS_SHIFT)
#define CH02_CARRIER_DCO_PHASE           ((CH02_CONTROL+CARRIER_DCO_PHASE)>>ADDRESS_SHIFT)
#define CH02_EPOCH_COUNT                 ((CH02_CONTROL+EPOCH_COUNT)>>ADDRESS_SHIFT)
#define CH02_CODE_DCO_PHASE              ((CH02_CONTROL+CODE_DCO_PHASE)>>ADDRESS_SHIFT)
#define CH02_CARRIER_CYCLE_COUNTER_HIGH  ((CH02_CONTROL+CARRIER_CYCLE_COUNTER_HIGH)>>ADDRESS_SHIFT)
#define CH02_EPOCH_CHECK                 ((CH02_CONTROL+EPOCH_CHECK)>>ADDRESS_SHIFT)
            
/* Write */

#define CH02_SATCNTL                     ((CH02_CONTROL+SATCNTL)>>ADDRESS_SHIFT)
#define CH02_CODE_PHASE_COUNTER          ((CH02_CONTROL+CODE_PHASE_COUNTER)>>ADDRESS_SHIFT)
#define CH02_CARRIER_CYCLE_COUNTER       ((CH02_CONTROL+CARRIER_CYCLE_COUNTER)>>ADDRESS_SHIFT)
#define CH02_CARRIER_DCO_INCR_HIGH       ((CH02_CONTROL+CARRIER_DCO_INCR_HIGH)>>ADDRESS_SHIFT)
#define CH02_CARRIER_DCO_INCR_LOW        ((CH02_CONTROL+CARRIER_DCO_INCR_LOW)>>ADDRESS_SHIFT)
#define CH02_CODE_DCO_INCR_HIGH          ((CH02_CONTROL+CODE_DCO_INCR_HIGH)>>ADDRESS_SHIFT)
#define CH02_CODE_DCO_INCR_LOW           ((CH02_CONTROL+CODE_DCO_INCR_LOW)>>ADDRESS_SHIFT)
#define CH02_EPOCH_LOAD                  ((CH02_CONTROL+EPOCH_LOAD)>>ADDRESS_SHIFT)

/* Read */

#define CH03_CODE_SLEW_READ              ((CH03_CONTROL+CODE_SLEW_READ)>>ADDRESS_SHIFT)
#define CH03_CODE_PHASE                  ((CH03_CONTROL+CODE_PHASE)>>ADDRESS_SHIFT)
#define CH03_CARRIER_CYCLE_COUNTER_LOW   ((CH03_CONTROL+CARRIER_CYCLE_COUNTER_LOW)>>ADDRESS_SHIFT)
#define CH03_CARRIER_DCO_PHASE           ((CH03_CONTROL+CARRIER_DCO_PHASE)>>ADDRESS_SHIFT)
#define CH03_EPOCH_COUNT                 ((CH03_CONTROL+EPOCH_COUNT)>>ADDRESS_SHIFT)
#define CH03_CODE_DCO_PHASE              ((CH03_CONTROL+CODE_DCO_PHASE)>>ADDRESS_SHIFT)
#define CH03_CARRIER_CYCLE_COUNTER_HIGH  ((CH03_CONTROL+CARRIER_CYCLE_COUNTER_HIGH)>>ADDRESS_SHIFT)
#define CH03_EPOCH_CHECK                 ((CH03_CONTROL+EPOCH_CHECK)>>ADDRESS_SHIFT)

/* Write */

#define CH03_SATCNTL                     ((CH03_CONTROL+SATCNTL)>>ADDRESS_SHIFT)
#define CH03_CODE_PHASE_COUNTER          ((CH03_CONTROL+CODE_PHASE_COUNTER)>>ADDRESS_SHIFT)
#define CH03_CARRIER_CYCLE_COUNTER       ((CH03_CONTROL+CARRIER_CYCLE_COUNTER)>>ADDRESS_SHIFT)
#define CH03_CARRIER_DCO_INCR_HIGH       ((CH03_CONTROL+CARRIER_DCO_INCR_HIGH)>>ADDRESS_SHIFT)
#define CH03_CARRIER_DCO_INCR_LOW        ((CH03_CONTROL+CARRIER_DCO_INCR_LOW)>>ADDRESS_SHIFT)
#define CH03_CODE_DCO_INCR_HIGH          ((CH03_CONTROL+CODE_DCO_INCR_HIGH)>>ADDRESS_SHIFT)
#define CH03_CODE_DCO_INCR_LOW           ((CH03_CONTROL+CODE_DCO_INCR_LOW)>>ADDRESS_SHIFT)
#define CH03_EPOCH_LOAD                  ((CH03_CONTROL+EPOCH_LOAD)>>ADDRESS_SHIFT)

/* Read */

#define CH04_CODE_SLEW_READ              ((CH04_CONTROL+CODE_SLEW_READ)>>ADDRESS_SHIFT)
#define CH04_CODE_PHASE                  ((CH04_CONTROL+CODE_PHASE)>>ADDRESS_SHIFT)
#define CH04_CARRIER_CYCLE_COUNTER_LOW   ((CH04_CONTROL+CARRIER_CYCLE_COUNTER_LOW)>>ADDRESS_SHIFT)
#define CH04_CARRIER_DCO_PHASE           ((CH04_CONTROL+CARRIER_DCO_PHASE)>>ADDRESS_SHIFT)
#define CH04_EPOCH_COUNT                 ((CH04_CONTROL+EPOCH_COUNT)>>ADDRESS_SHIFT)
#define CH04_CODE_DCO_PHASE              ((CH04_CONTROL+CODE_DCO_PHASE)>>ADDRESS_SHIFT)
#define CH04_CARRIER_CYCLE_COUNTER_HIGH  ((CH04_CONTROL+CARRIER_CYCLE_COUNTER_HIGH)>>ADDRESS_SHIFT)
#define CH04_EPOCH_CHECK                 ((CH04_CONTROL+EPOCH_CHECK)>>ADDRESS_SHIFT)

/* Write */

#define CH04_SATCNTL                     ((CH04_CONTROL+SATCNTL)>>ADDRESS_SHIFT)
#define CH04_CODE_PHASE_COUNTER          ((CH04_CONTROL+CODE_PHASE_COUNTER)>>ADDRESS_SHIFT)
#define CH04_CARRIER_CYCLE_COUNTER       ((CH04_CONTROL+CARRIER_CYCLE_COUNTER)>>ADDRESS_SHIFT)
#define CH04_CARRIER_DCO_INCR_HIGH       ((CH04_CONTROL+CARRIER_DCO_INCR_HIGH)>>ADDRESS_SHIFT)
#define CH04_CARRIER_DCO_INCR_LOW        ((CH04_CONTROL+CARRIER_DCO_INCR_LOW)>>ADDRESS_SHIFT)
#define CH04_CODE_DCO_INCR_HIGH          ((CH04_CONTROL+CODE_DCO_INCR_HIGH)>>ADDRESS_SHIFT)
#define CH04_CODE_DCO_INCR_LOW           ((CH04_CONTROL+CODE_DCO_INCR_LOW)>>ADDRESS_SHIFT)
#define CH04_EPOCH_LOAD                  ((CH04_CONTROL+EPOCH_LOAD)>>ADDRESS_SHIFT)

/* Read */

#define CH05_CODE_SLEW_READ              ((CH05_CONTROL+CODE_SLEW_READ)>>ADDRESS_SHIFT)
#define CH05_CODE_PHASE                  ((CH05_CONTROL+CODE_PHASE)>>ADDRESS_SHIFT)
#define CH05_CARRIER_CYCLE_COUNTER_LOW   ((CH05_CONTROL+CARRIER_CYCLE_COUNTER_LOW)>>ADDRESS_SHIFT)
#define CH05_CARRIER_DCO_PHASE           ((CH05_CONTROL+CARRIER_DCO_PHASE)>>ADDRESS_SHIFT)
#define CH05_EPOCH_COUNT                 ((CH05_CONTROL+EPOCH_COUNT)>>ADDRESS_SHIFT)
#define CH05_CODE_DCO_PHASE              ((CH05_CONTROL+CODE_DCO_PHASE)>>ADDRESS_SHIFT)
#define CH05_CARRIER_CYCLE_COUNTER_HIGH  ((CH05_CONTROL+CARRIER_CYCLE_COUNTER_HIGH)>>ADDRESS_SHIFT)
#define CH05_EPOCH_CHECK                 ((CH05_CONTROL+EPOCH_CHECK)>>ADDRESS_SHIFT)

/* Write */

#define CH05_SATCNTL                     ((CH05_CONTROL+SATCNTL)>>ADDRESS_SHIFT)
#define CH05_CODE_PHASE_COUNTER          ((CH05_CONTROL+CODE_PHASE_COUNTER)>>ADDRESS_SHIFT)
#define CH05_CARRIER_CYCLE_COUNTER       ((CH05_CONTROL+CARRIER_CYCLE_COUNTER)>>ADDRESS_SHIFT)
#define CH05_CARRIER_DCO_INCR_HIGH       ((CH05_CONTROL+CARRIER_DCO_INCR_HIGH)>>ADDRESS_SHIFT)
#define CH05_CARRIER_DCO_INCR_LOW        ((CH05_CONTROL+CARRIER_DCO_INCR_LOW)>>ADDRESS_SHIFT)