m68bus.vhd

用VHDL控制LCD1602的源程序

--功能：M68总线操作时序
--作者：YBK
--时间：20008－03
--版本：1.0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity  M68BUS is
   port (
         CLK50: in std_logic;
     	 BufAddr	: in STD_LOGIC_VECTOR(4 downto 0);--column 0 to 31
	 	 Buf_DATA	: in STD_LOGIC_VECTOR(7 downto 0);--data
     	 Buf_WREN	: in STD_LOGIC;--write data to display buffer when WriteEN = 0;
         --对外信号
         RW: out std_logic;--读写线低写，高读
         RS: out std_logic;--指令数据控制线 低指令，高数据
         EN: out std_logic;--读写操作 正脉冲
         D8: out std_logic_vector(7 downto 0)--数据线 8位
        );
end M68BUS;

architecture M68BUSARCH of M68BUS is
signal DivCounter: integer range 0 to 1023;
signal CLK		: std_logic;
signal BusRwCLK : std_logic;
signal BusEnCLK : std_logic;
signal TempRW   : std_logic;
signal TempRS   : std_logic;

signal  OpStatus: std_logic_vector(7 downto 0);
signal  DisCounter : integer range 0 to 31;
--display buffer
type BUF is array(0 to 31) of STD_LOGIC_VECTOR(7 downto 0);
signal DisBuf : BUF;

--状态机常量定义
constant IDLE           : std_logic_vector(7 downto 0)  :=X"00";
constant DisplayClear   : std_logic_vector(7 downto 0)  :=X"01";--清屏并光标复位
constant CursorHome     : std_logic_vector(7 downto 0)  :=X"02";--光标复位
constant DisplayMode    : std_logic_vector(7 downto 0)  :=X"06";--设置显示模式
constant DisplayON      : std_logic_vector(7 downto 0)  :=X"0C";--显示器开
constant DisplayShift   : std_logic_vector(7 downto 0)  :=X"14";--文字光标
constant FunctionSet    : std_logic_vector(7 downto 0)  :=X"38";--点阵显示模式
constant CDRAMSetting1  : std_logic_vector(7 downto 0)  :=X"80";
constant CDRAMSetting2  : std_logic_vector(7 downto 0)  :=X"C0";
constant CDRAMWrite     : std_logic_vector(7 downto 0)  :=X"40";

begin
-------------------------------------------------
process(CLK50)
begin
	if(CLK50'event and CLK50='1') then	
		if(DivCounter = 1000) then
		 	DivCounter <=0;
			CLK <= not CLK;
		else
			DivCounter <= DivCounter + 1;
		end if;
		--
		if Buf_WREN = '0' then--3
     		DisBuf(CONV_INTEGER(BufAddr)) <= Buf_DATA;
		end if;
	end if;
end process;
-----------------产生读写时钟--------------------
process(CLK)
begin
           if(CLK'event and CLK='1') then
                        BusRwCLK <= not BusRwCLK;
           end if;
		   if(CLK'event and CLK='0') then
                        BusEnCLK <= not BusEnCLK;
           end if;
end process;
--信号状态
EN <= BusEnCLK;
RW <= '0';
RS <= '1' when OpStatus = CDRAMWrite else
      '0';
D8 <= DisplayClear  	when OpStatus = DisplayClear  else
      CursorHome    	when OpStatus = CursorHome    else
      DisplayMode   	when OpStatus = DisplayMode   else
      DisplayON     	when OpStatus = DisplayON     else
      DisplayShift  	when OpStatus = DisplayShift  else
      FunctionSet   	when OpStatus = FunctionSet   else
      CDRAMSetting1 	when OpStatus = CDRAMSetting1 else
	  CDRAMSetting2 	when OpStatus = CDRAMSetting2 else
      DisBuf(DisCounter)when OpStatus = CDRAMWrite    else
      X"00";
-------------------------------------------------
process(BusRwCLK)
begin
   if(BusRwCLK'event and BusRwCLK = '1') then
     case OpStatus is
     when IDLE          => OpStatus <= DisplayClear;DisCounter<=0;
     when DisplayClear  => OpStatus <= CursorHome;
     when CursorHome    => OpStatus <= DisplayMode;
     when DisplayMode   => OpStatus <= DisplayON;
     when DisplayON     => OpStatus <= DisplayShift;
     when DisplayShift  => OpStatus <= FunctionSet;
     when FunctionSet   => OpStatus <= CDRAMSetting1;
     when CDRAMSetting1 => OpStatus <= CDRAMWrite;
     when CDRAMWrite    => DisCounter <= DisCounter +1;
						   if(DisCounter = 15) then
							 OpStatus <= CDRAMSetting2;
						   elsif(DisCounter = 31) then
							 OpStatus <= CDRAMSetting1;
						   end if;
	 when CDRAMSetting2 => OpStatus <= CDRAMWrite;
     when others        => OpStatus <= IDLE;
     end case;
  end if;
end process;

end M68BUSARCH;