lcdtest.vhd

用VHDL控制LCD1602的源程序

--功能：LCD测试程序
--作者：YBK
--时间：20008－03
--版本：1.0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY LCDTest IS
	PORT
	(
	 clk		: in STD_LOGIC; --system clock
	 Reset		: in STD_LOGIC;  --system Reset
	
	 RW		: out STD_LOGIC;--0:write; 1:read;
	 RS		: out STD_LOGIC;--0:Command; 1:data;
	 EN		: out STD_LOGIC;--Operate valid on falling edge;
	 D8	: out STD_LOGIC_VECTOR(7 downto 0)--data to VFD
	);
END LCDTest;

ARCHITECTURE LCDOperation_a OF LCDTest IS

component M68BUS
	PORT
	(
         CLK50: in std_logic;
     	 BufAddr	: in STD_LOGIC_VECTOR(4 downto 0);--column 0 to 31
	 	 Buf_DATA	: in STD_LOGIC_VECTOR(7 downto 0);--data
     	 Buf_WREN	: in STD_LOGIC;--write data to display buffer when WriteEN = 0;
         --对外信号
         RW: out std_logic;--读写线低写，高读
         RS: out std_logic;--指令数据控制线 低指令，高数据
         EN: out std_logic;--读写操作 正脉冲
         D8: out std_logic_vector(7 downto 0)--数据线 8位
	);
end component;

signal Bufindex : STD_LOGIC_VECTOR(4 downto 0);
signal DisChar  : STD_LOGIC_VECTOR(7 downto 0); 
signal Writebuf  : STD_LOGIC;

signal Counter  : integer range 0 to 32;
BEGIN

Module1 : M68BUS port map
  (
	 CLK50		=> clk,
	 BufAddr	=> Bufindex,
	 Buf_DATA	=> DisChar+Bufindex,
     Buf_WREN	=> Writebuf,
-------------------------------------------------------
     RW		=> RW,
	 RS		=> RS,
	 EN		=> EN,
	 D8		=> D8 
  );

Writebuf  <= '0';

process(clk,Reset)
 begin
   if(clk'event and clk='1') then--1

   if(Reset = '0')then--3
   	Bufindex <="00000";
   	DisChar <= DisChar + '1';	
   else
	Bufindex  <= Bufindex + '1';
   end if;--3	

   end if;--1
 end process;
END LCDOperation_a;