_primary.vhd

来自「xilinx ISE 实例代码。可用ISE直接打开」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity proc is
    port(
        clk             : in     vl_logic;
        addr            : out    vl_logic_vector(7 downto 0);
        data            : inout  vl_logic_vector(15 downto 0);
        rw              : out    vl_logic;
        strb            : out    vl_logic;
        rdy             : in     vl_logic
    );
end proc;