picoblaze_hc164_busif.v

xilinx ISE 实例代码。可用ISE直接打开

module picoblaze_hc164_busif(

  iCLK,
  iRST_N,
  iADDR,
  iDATAIN,
  iWR,
  iRD,
  oHC_DBUS,
  
  oLED_VAL,
  oSEG_VAL,
  oSEG_DOT


);

parameter C_BASEADDR = 8'h00;


input         iCLK     ;  // System clock
input         iRST_N   ;  // System RST Low Active
input [ 7: 0] iADDR    ;  // Address Bus 8 bits
input [ 7: 0] iDATAIN  ;  // Data Bus input 8 bits
input         iWR      ;  // Write operation
input         iRD      ;  // Read operation 
output[ 7: 0] oHC_DBUS ;  // Data Bus output 8 bits


output[ 3: 0] oLED_VAL;
output[15: 0] oSEG_VAL;
output[ 3: 0] oSEG_DOT;



reg [ 3: 0] sr_ledvalue    ; // offset 0x0     
reg [ 7: 0] sr_segvalue_up ; // offset 0x1
reg [ 7: 0] sr_segvalue_low; // offset 0x2
reg [ 3: 0] sr_segdot      ; // offset 0x3
reg [ 7: 0] sr_HC_DBUS       ;

reg         sr_wr;
reg         sr_rd;



wire s_ADDRMATCH_LEDVAL;
wire s_ADDRMATCH_SEGVAL_UP;
wire s_ADDRMATCH_SEGVAL_LOW;
wire s_ADDRMATCH_SEGDOT;

wire s_RD;
wire s_WR;


assign oLED_VAL[ 3: 0] = sr_ledvalue[ 3: 0];
assign oSEG_VAL[15: 0] = { sr_segvalue_up[ 7: 0],sr_segvalue_low[ 7: 0]};
assign oSEG_DOT[ 3: 0] = sr_segdot[ 3: 0];

assign oHC_DBUS = sr_HC_DBUS;// & { 8{s_RD}};


assign s_ADDRMATCH_LEDVAL     = (iADDR == C_BASEADDR       )? 1'b1:1'b0;
assign s_ADDRMATCH_SEGVAL_UP  = (iADDR == C_BASEADDR + 8'h1)? 1'b1:1'b0;
assign s_ADDRMATCH_SEGVAL_LOW = (iADDR == C_BASEADDR + 8'h2)? 1'b1:1'b0;
assign s_ADDRMATCH_SEGDOT     = (iADDR == C_BASEADDR + 8'h3)? 1'b1:1'b0;

assign s_WR = iWR & (~sr_wr);
assign s_RD = iRD & (~sr_rd);



always @ (
  s_ADDRMATCH_LEDVAL     or
  s_ADDRMATCH_SEGVAL_UP  or
  s_ADDRMATCH_SEGVAL_LOW or
  s_ADDRMATCH_SEGDOT     or
  oHC_DBUS               or
  sr_ledvalue            or
  sr_segvalue_up         or
  sr_segvalue_low        or
//  s_RD                   or
  iRD                    or
  sr_segdot
) begin
//  if ( s_RD) begin
    case ({s_ADDRMATCH_LEDVAL,s_ADDRMATCH_SEGVAL_UP,s_ADDRMATCH_SEGVAL_LOW,s_ADDRMATCH_SEGDOT})
      4'b1000: begin
        sr_HC_DBUS = {4'h0,sr_ledvalue};
      end
      4'b0100: begin
        sr_HC_DBUS = sr_segvalue_up[ 7: 0] ;
      end
      4'b0010: begin
        sr_HC_DBUS = sr_segvalue_low[ 7: 0];
      end
      4'b0001: begin
        sr_HC_DBUS = {4'h0,sr_segdot[ 3: 0]};
      end
      default: begin
        sr_HC_DBUS = 8'h0;               
      end  
    endcase
//  end
end



// register sr_wr
always @ ( posedge iCLK or negedge iRST_N ) begin
  if ( !iRST_N ) begin
    sr_wr <= 1'b0;	
  end
  else begin
    sr_wr <= iWR; 
  end
end

// register sr_rd  
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_rd <= 1'b0;	
  end
  else begin
    sr_rd <= iRD;
  end
end

// register sr_ledvalue
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_ledvalue <= 4'h0;	
  end
  else begin
    if ( s_ADDRMATCH_LEDVAL & s_WR ) begin
      sr_ledvalue <= iDATAIN[ 3: 0];
    end
    else begin
      sr_ledvalue <= sr_ledvalue;
    end
  end
end

// register sr_segvalue_up
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_segvalue_up <= 8'h0;	
  end
  else begin
    if ( s_ADDRMATCH_SEGVAL_UP & s_WR ) begin
      sr_segvalue_up <= iDATAIN[ 7: 0];
    end
    else begin
      sr_segvalue_up <= sr_segvalue_up;
    end
  end
end

// register sr_segvalue_low
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_segvalue_low <= 8'h0;	
  end
  else begin
    if ( s_ADDRMATCH_SEGVAL_LOW & s_WR ) begin
      sr_segvalue_low <= iDATAIN[ 7: 0];
    end
    else begin
      sr_segvalue_low <= sr_segvalue_low;
    end
  end
end

// register sr_segdot
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_segdot <= 4'h0;	
  end
  else begin
    if ( s_ADDRMATCH_SEGDOT & s_WR ) begin
      sr_segdot <= iDATAIN[ 3: 0];
    end
    else begin
      sr_segdot <= sr_segdot;
    end
  end
end

endmodule