picoblaze_pushbutton_busif.v

xilinx ISE 实例代码。可用ISE直接打开

module picoblaze_pushbutton_busif(

  iCLK,
  iRST_N,
  iADDR,
  iDATAIN,
  iWR,
  iRD,
  iPUSHBUTTON,
  oHC_DBUS,
  
  oISR  
  

);

parameter C_BASEADDR = 8'h00;


input         iCLK     ;  // System clock
input         iRST_N   ;  // System RST Low Active
input [ 7: 0] iADDR    ;  // Address Bus 8 bits
input [ 7: 0] iDATAIN  ;  // Data Bus input 8 bits
input         iWR      ;  // Write operation
input         iRD      ;  // Read operation 

input [ 3: 0] iPUSHBUTTON;
output[ 7: 0] oHC_DBUS ;  // Data Bus output 8 bits
output[ 3: 0] oISR     ; 
 



reg [ 3: 0] sr_isr;  // offset 0x0     


reg [ 7: 0] sr_HC_DBUS       ;

reg         sr_wr;
reg         sr_rd;

wire s_ADDRMATCH_ISR;

wire s_RD;
wire s_WR;
                                   
assign oHC_DBUS = sr_HC_DBUS;// & { 8{s_RD}};
assign oISR     = sr_isr;

assign s_ADDRMATCH_ISR    = (iADDR == C_BASEADDR       )? 1'b1:1'b0;

assign s_WR = iWR & (~sr_wr);
assign s_RD = iRD & (~sr_rd);



always @ (
  s_ADDRMATCH_ISR   or
  oHC_DBUS          or
  sr_isr            or
  iRD               
)begin
  case ({s_ADDRMATCH_ISR})
    1'b1: begin
      sr_HC_DBUS = {4'h0,sr_isr};
    end
    1'b0: begin
      sr_HC_DBUS = 8'h0;
    end
  endcase
end



// register sr_wr
always @ ( posedge iCLK or negedge iRST_N ) begin
  if ( !iRST_N ) begin
    sr_wr <= 1'b0;	
  end
  else begin
    sr_wr <= iWR; 
  end
end

// register sr_rd  
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_rd <= 1'b0;	
  end
  else begin
    sr_rd <= iRD;
  end
end

// register sr_isr
always @ ( posedge iCLK or negedge iRST_N  ) begin
  if ( !iRST_N ) begin
    sr_isr <= 4'h0;	
  end
  else begin
    if ( s_ADDRMATCH_ISR & s_WR ) begin
      sr_isr <= iDATAIN[ 3: 0];
    end
    else begin
      sr_isr <= sr_isr | { ~iPUSHBUTTON[3],~iPUSHBUTTON[2],~iPUSHBUTTON[1],~iPUSHBUTTON[0]} ;
    end
  end
end
endmodule