_primary.vhd

来自「xilinx ISE 实例代码。可用ISE直接打开」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity \dp_syn_ram-rtl\ is
    generic(
        data_width      : integer := 8;
        addr_width      : integer := 3
    );
    port(
        inaddr          : in     vl_logic_vector;
        outaddr         : in     vl_logic_vector;
        data_in         : in     vl_logic_vector;
        inclk           : in     vl_logic;
        outclk          : in     vl_logic;
        we              : in     vl_logic;
        data_out        : out    vl_logic_vector
    );
end \dp_syn_ram-rtl\;