jc2_top.syr

xilinx ISE 实例代码。可用ISE直接打开

Release 9.1i - xst J.30
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> PMSPEC -- Overriding Xilinx file <d:/Xilinx91i/acecf/data/acecf.acd> with local file <D:/Xilinx91i/acecf/data/acecf.acd>
Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 2.23 s | Elapsed : 0.00 / 2.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 2.25 s | Elapsed : 0.00 / 2.00 s
 
--> Reading design: jc2_top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "jc2_top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "jc2_top"
Output Format                      : NGC
Target Device                      : xc3s400-5-pq208

---- Source Options
Top Module Name                    : jc2_top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : jc2_top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
async_to_sync                      : NO
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "jc2_top.v" in library work
Module <jc2_top> compiled
No errors in compilation
Analysis of file <"jc2_top.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <jc2_top> in library <work>.


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <jc2_top>.
Module <jc2_top> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <jc2_top>.
    Related source file is "jc2_top.v".
    Found 4-bit register for signal <q>.
    Found 1-bit register for signal <dir>.
    Found 1-bit register for signal <run>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <jc2_top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 6
 1-bit register                                        : 6

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '3s400.nph' in environment D:\Xilinx91i;d:\Xilinx91i.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 6
 Flip-Flops                                            : 6

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <jc2_top> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block jc2_top, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 6
 Flip-Flops                                            : 6

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : jc2_top.ngr
Top Level Output File Name         : jc2_top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 8

Cell Usage :
# BELS                             : 9
#      INV                         : 2
#      LUT3                        : 4
#      LUT3_D                      : 1
#      LUT4                        : 1
#      VCC                         : 1
# FlipFlops/Latches                : 6
#      FD                          : 1
#      FDE                         : 4
#      FDRE                        : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 7
#      IBUF                        : 3
#      OBUF                        : 4
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                       4  out of   3584     0%  
 Number of Slice Flip Flops:             6  out of   7168     0%  
 Number of 4 input LUTs:                 8  out of   7168     0%  
 Number of IOs:                          8
 Number of bonded IOBs:                  8  out of    141     5%  
 Number of GCLKs:                        1  out of      8    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 6     |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 3.330ns (Maximum Frequency: 300.318MHz)
   Minimum input arrival time before clock: 3.745ns
   Maximum output required time after clock: 6.314ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 3.330ns (frequency: 300.318MHz)
  Total number of paths / destination ports: 17 / 9
-------------------------------------------------------------------------
Delay:               3.330ns (Levels of Logic = 2)
  Source:            dir (FF)
  Destination:       q_3 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: dir to q_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             1   0.626   0.740  dir (dir)
     LUT3_D:I2->O          3   0.479   0.830  _old_dir_21 (_old_dir_2)
     LUT3:I2->O            1   0.479   0.000  q_1_mux00001 (q_1_mux0000)
     FDE:D                     0.176          q_1
    ----------------------------------------
    Total                      3.330ns (1.760ns logic, 1.570ns route)
                                       (52.9% logic, 47.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 25 / 11
-------------------------------------------------------------------------
Offset:              3.745ns (Levels of Logic = 3)
  Source:            right (PAD)
  Destination:       q_3 (FF)
  Destination Clock: clk rising

  Data Path: right to q_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   0.715   1.066  right_IBUF (right_IBUF)
     LUT3_D:I0->O          3   0.479   0.830  _old_dir_21 (_old_dir_2)
     LUT3:I2->O            1   0.479   0.000  q_1_mux00001 (q_1_mux0000)
     FDE:D                     0.176          q_1
    ----------------------------------------
    Total                      3.745ns (1.849ns logic, 1.896ns route)
                                       (49.4% logic, 50.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              6.314ns (Levels of Logic = 1)
  Source:            q_2 (FF)
  Destination:       q<2> (PAD)
  Source Clock:      clk rising

  Data Path: q_2 to q<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              4   0.626   0.779  q_2 (q_2)
     OBUF:I->O                 4.909          q_2_OBUF (q<2>)
    ----------------------------------------
    Total                      6.314ns (5.535ns logic, 0.779ns route)
                                       (87.7% logic, 12.3% route)

=========================================================================
CPU : 12.06 / 14.47 s | Elapsed : 12.00 / 14.00 s
 
--> 

Total memory usage is 121152 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)