_primary.vhd

来自「xilinx ISE 实例代码。可用ISE直接打开」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity beh_sram is
    generic(
        M_DLY           : integer := 9
    );
    port(
        clk             : in     vl_logic;
        dat             : inout  vl_logic_vector(31 downto 0);
        addr            : in     vl_logic_vector(9 downto 0);
        \rd_\           : in     vl_logic;
        \wr_\           : in     vl_logic
    );
end beh_sram;