firpall.tan.rpt

FIR低通滤波器得设计

; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                            ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk                          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                    ; To                                                                                                                                                                              ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 112.36 MHz ( period = 8.900 ns )                    ; mult16:inst6|lpm_mult0:inst13|lpm_mult:lpm_mult_component|multcore:mult_core|altshift_taps:decoder_node_rtl_1|shift_taps_vbk:auto_generated|cntr_0fc:cntr1|safe_q[0]                                    ; mult16:inst6|lpm_mult0:inst13|lpm_mult:lpm_mult_component|multcore:mult_core|altshift_taps:decoder_node_rtl_1|shift_taps_vbk:auto_generated|cntr_0fc:cntr1|safe_q[1]            ; clk        ; clk      ; None                        ; None                      ; 8.698 ns                ;
; N/A                                     ; 112.36 MHz ( period = 8.900 ns )                    ; mult16:inst6|lpm_mult0:inst13|lpm_mult:lpm_mult_component|multcore:mult_core|altshift_taps:decoder_node_rtl_1|shift_taps_vbk:auto_generated|cntr_0fc:cntr1|safe_q[0]                                    ; mult16:inst6|lpm_mult0:inst13|lpm_mult:lpm_mult_component|multcore:mult_core|altshift_taps:decoder_node_rtl_1|shift_taps_vbk:auto_generated|cntr_0fc:cntr1|safe_q[0]            ; clk        ; clk      ; None                        ; None                      ; 8.698 ns                ;
; N/A                                     ; 117.56 MHz ( period = 8.506 ns )                    ; mult16:inst6|lpm_mult0:inst13|lpm_mult:lpm_mult_component|multcore:mult_core|altshift_taps:decoder_node_rtl_1|shift_taps_vbk:auto_generated|cntr_0fc:cntr1|safe_q[1]                                    ; mult16:inst6|lpm_mult0:inst13|lpm_mult:lpm_mult_component|multcore:mult_core|altshift_taps:decoder_node_rtl_1|shift_taps_vbk:auto_generated|cntr_0fc:cntr1|safe_q[1]            ; clk        ; clk      ; None                        ; None                      ; 8.304 ns                ;
; N/A                                     ; 117.56 MHz ( period = 8.506 ns )                    ; mult16:inst6|lpm_mult0:inst13|lpm_mult:lpm_mult_component|multcore:mult_core|altshift_taps:decoder_node_rtl_1|shift_taps_vbk:auto_generated|cntr_0fc:cntr1|safe_q[1]                                    ; mult16:inst6|lpm_mult0:inst13|lpm_mult:lpm_mult_component|multcore:mult_core|altshift_taps:decoder_node_rtl_1|shift_taps_vbk:auto_generated|cntr_0fc:cntr1|safe_q[0]            ; clk        ; clk      ; None                        ; None                      ; 8.304 ns                ;
; N/A                                     ; 153.05 MHz ( period = 6.534 ns )                    ; parallel_add0:inst5|parallel_add:parallel_add_component|par_add_8ve:auto_generated|altshift_taps:dffe267_rtl_0|shift_taps_akg:auto_generated|cntr_0fc:cntr1|safe_q[0]                                   ; parallel_add0:inst5|parallel_add:parallel_add_component|par_add_8ve:auto_generated|altshift_taps:dffe267_rtl_0|shift_taps_akg:auto_generated|cntr_0fc:cntr1|safe_q[1]           ; clk        ; clk      ; None                        ; None                      ; 6.332 ns                ;
; N/A                                     ; 153.05 MHz ( period = 6.534 ns )                    ; parallel_add0:inst5|parallel_add:parallel_add_component|par_add_8ve:auto_generated|altshift_taps:dffe267_rtl_0|shift_taps_akg:auto_generated|cntr_0fc:cntr1|safe_q[0]                                   ; parallel_add0:inst5|parallel_add:parallel_add_component|par_add_8ve:auto_generated|altshift_taps:dffe267_rtl_0|shift_taps_akg:auto_generated|cntr_0fc:cntr1|safe_q[0]           ; clk        ; clk      ; None                        ; None                      ; 6.332 ns                ;
; N/A                                     ; 164.34 MHz ( period = 6.085 ns )                    ; parallel_add0:inst5|parallel_add:parallel_add_component|par_add_8ve:auto_generated|altshift_taps:dffe267_rtl_0|shift_taps_akg:auto_generated|cntr_0fc:cntr1|safe_q[1]                                   ; parallel_add0:inst5|parallel_add:parallel_add_component|par_add_8ve:auto_generated|altshift_taps:dffe267_rtl_0|shift_taps_akg:auto_generated|cntr_0fc:cntr1|safe_q[1]           ; clk        ; clk      ; None                        ; None                      ; 5.883 ns                ;
; N/A                                     ; 164.34 MHz ( period = 6.085 ns )                    ; parallel_add0:inst5|parallel_add:parallel_add_component|par_add_8ve:auto_generated|altshift_taps:dffe267_rtl_0|shift_taps_akg:auto_generated|cntr_0fc:cntr1|safe_q[1]                                   ; parallel_add0:inst5|parallel_add:parallel_add_component|par_add_8ve:auto_generated|altshift_taps:dffe267_rtl_0|shift_taps_akg:auto_generated|cntr_0fc:cntr1|safe_q[0]           ; clk        ; clk      ; None                        ; None                      ; 5.883 ns                ;
; N/A                                     ; 202.47 MHz ( period = 4.939 ns )                    ; mult16:inst6|lpm_mult0:inst9|lpm_mult:lpm_mult_component|altshift:external_latency_ffs|points[1][2]                                                                                                     ; parallel_add0:inst5|parallel_add:parallel_add_component|par_add_8ve:auto_generated|dffe248                                                                                      ; clk        ; clk      ; None                        ; None                      ; 4.694 ns                ;
; N/A                                     ; 202.47 MHz ( period = 4.939 ns )                    ; mult16:inst6|lpm_mult0:inst9|lpm_mult:lpm_mult_component|altshift:external_latency_ffs|points[1][2]                                                                                                     ; parallel_add0:inst5|parallel_add:parallel_add_component|par_add_8ve:auto_generated|dffe224                                                                                      ; clk        ; clk      ; None                        ; None                      ; 4.694 ns                ;