firpall.tan.rpt

FIR低通滤波器得设计

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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                 ; To                                                                                                                                                                                                    ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 5.759 ns                         ; data[0]                                                                                                                                                              ; mult16:inst6|lpm_mult0:inst13|lpm_mult:lpm_mult_component|multcore:mult_core|altshift_taps:decoder_node_rtl_1|shift_taps_vbk:auto_generated|altsyncram_itu:altsyncram2|ram_block3a0~porta_datain_reg1 ;                              ; clk                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 6.522 ns                         ; parallel_add0:inst5|parallel_add:parallel_add_component|par_add_8ve:auto_generated|dffe1                                                                             ; pallFIR[0]                                                                                                                                                                                            ; clk                          ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 1.634 ns                         ; altera_internal_jtag~TDO                                                                                                                                             ; altera_reserved_tdo                                                                                                                                                                                   ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 2.847 ns                         ; altera_internal_jtag                                                                                                                                                 ; mult16:inst6|lpm_constant1:inst34|lpm_constant:lpm_constant_component|lpm_constant_ug8:ag|sld_mod_ram_rom:mgl_prim1|bypass_reg_out                                                                    ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 64.31 MHz ( period = 15.550 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:12:IRF|Q[2]                                                                                                                  ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                                                                                                                     ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk'                          ; N/A   ; None          ; 112.36 MHz ( period = 8.900 ns ) ; mult16:inst6|lpm_mult0:inst13|lpm_mult:lpm_mult_component|multcore:mult_core|altshift_taps:decoder_node_rtl_1|shift_taps_vbk:auto_generated|cntr_0fc:cntr1|safe_q[0] ; mult16:inst6|lpm_mult0:inst13|lpm_mult:lpm_mult_component|multcore:mult_core|altshift_taps:decoder_node_rtl_1|shift_taps_vbk:auto_generated|cntr_0fc:cntr1|safe_q[0]                                  ; clk                          ; clk                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                                                      ;                                                                                                                                                                                                       ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C4F324C6        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;