shift_taps_akg.tdf

FIR低通滤波器得设计

--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" NUMBER_OF_TAPS=1 TAP_DISTANCE=3 WIDTH=33 clock shiftin taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 4.2 cbx_altdpram 2004:08:15:21:15:28:SJ cbx_altshift_taps 2004:08:15:21:15:58:SJ cbx_altsyncram 2004:11:16:15:31:02:SJ cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:10:18:11:29:46:SJ cbx_lpm_counter 2004:10:25:23:03:40:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_lpm_mux 2004:08:15:21:16:24:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:09:29:16:04:00:SJ  VERSION_END


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FUNCTION altsyncram_h4q (address_a[1..0], address_b[1..0], clock0, clock1, clocken0, clocken1, data_a[32..0], wren_a)
RETURNS ( q_b[32..0]);
FUNCTION add_sub_und (dataa[1..0], datab[1..0])
RETURNS ( result[1..0]);
FUNCTION cntr_0fc (clk_en, clock)
RETURNS ( q[1..0]);

--synthesis_resources = lut 8 M4K 1 
SUBDESIGN shift_taps_akg
( 
	clock	:	input;
	shiftin[32..0]	:	input;
	shiftout[32..0]	:	output;
	taps[32..0]	:	output;
) 
VARIABLE 
	altsyncram4 : altsyncram_h4q;
	dffe3a[1..0] : dffe;
	add_sub2 : add_sub_und;
	cntr1 : cntr_0fc;
	clken	: NODE;
	rdaddress[1..0]	: WIRE;

BEGIN 
	altsyncram4.address_a[] = cntr1.q[];
	altsyncram4.address_b[] = rdaddress[];
	altsyncram4.clock0 = clock;
	altsyncram4.clock1 = clock;
	altsyncram4.clocken0 = clken;
	altsyncram4.clocken1 = clken;
	altsyncram4.data_a[] = ( shiftin[]);
	altsyncram4.wren_a = B"1";
	dffe3a[].CLK = clock;
	dffe3a[].D = ( (! add_sub2.result[1..1]), add_sub2.result[0..0]);
	dffe3a[].ENA = clken;
	add_sub2.dataa[] = cntr1.q[];
	add_sub2.datab[] = B"00";
	cntr1.clk_en = clken;
	cntr1.clock = clock;
	clken = VCC;
	rdaddress[] = ( (! dffe3a[1..1].Q), dffe3a[0..0].Q);
	shiftout[32..0] = altsyncram4.q_b[32..0];
	taps[] = altsyncram4.q_b[];
END;
--VALID FILE